Datasheet > CY62126EV30LL-45BVXIT

CY62126EV30LL-45BVXIT

更新时间： 2024-09-14 11:10:03

品牌	Logo	应用领域
英飞凌 - INFINEON		静态存储器内存集成电路
页数	文件大小	规格书
18页	518K
描述
Asynchronous SRAM

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CY62126EV30 MoBL^®

1-Mbit (64 K × 16) Static RAM

1-Mbit (64

K × 16) Static RAM

Features

Functional Description

■ High speed: 45 ns

The CY62126EV30 is a high performance CMOS static RAM

organized as 64K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life(MoBL^®) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption when addresses are not toggling. Placing the

device in standby mode reduces power consumption by more

than 99 percent when deselected (CE HIGH). The input and

output pins (I/O₀through I/O₁₅) are placed in a high impedance

state when the device is deselected (CE HIGH), the outputs are

disabled (OE HIGH), both Byte High Enable and Byte Low

Enable are disabled (BHE, BLE HIGH) or during a write

operation (CE LOW and WE LOW).

■ Temperature ranges

❐ Industrial: –40 °C to +85 °C

❐ Automotive-A: –40 °C to +85 °C

❐ Automotive-E: –40 °C to +125 °C

■ Wide voltage range: 2.2 V to 3.6 V

■ Pin compatible with CY62126DV30

■ Ultra low standby power

❐ Typical standby current: 1 A

❐ Maximum standby current: 4 A

■ Ultra low active power

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from I/O pins (I/O₀through I/O₇) is written into the location

specified on the address pins (A₀through A₁₅). If Byte High

Enable (BHE) is LOW, then data from I/O pins (I/O₈through

I/O₁₅) is written into the location specified on the address pins

(A₀through A₁₅).

❐ Typical active current: 1.3 mA at f = 1 MHz

■ Easy memory expansion with CE and OE features

■ Automatic power down when deselected

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appear on I/O₀to I/O₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on I/O₈to I/O₁₅. See the Truth Table on page 11 for a

complete description of read and write modes.

■ Offered in Pb-free 48-ball very fine-pitch ball grid array

(VFBGA) and 44-pin thin small outline package (TSOP) II

packages

For a complete list of related documentation, click here.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

64K x 16

I/O₀–I/O₇

RAM Array

I/O₈–I/O₁₅

A₂

A₁

A₀

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document Number: 38-05486 Rev. *P

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised November 24, 2017

12 3 4 5 6 7...18

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与CY62126EV30LL-45BVXIT相关器件

型号	品牌	获取价格	描述	数据表
CY62126EV30LL-45ZSXA	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30LL-45ZSXA	INFINEON	获取价格	Asynchronous SRAM
CY62126EV30LL-45ZSXAT	CYPRESS	获取价格	Standard SRAM, 64KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62126EV30LL-45ZSXAT	INFINEON	获取价格	Asynchronous SRAM
CY62126EV30LL-45ZSXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30LL-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY62126EV30LL-45ZSXIT	CYPRESS	获取价格	暂无描述
CY62126EV30LL-45ZSXIT	INFINEON	获取价格	Asynchronous SRAM
CY62126EV30LL-55BVXE	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30LL-55BVXE	INFINEON	获取价格	Asynchronous SRAM

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