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CY62126EV30LL-45ZSXIT

更新时间： 2024-11-05 13:07:11
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赛普拉斯 - CYPRESS /
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CY62126EV30LL-45ZSXIT 数据手册

 浏览型号CY62126EV30LL-45ZSXIT的Datasheet PDF文件第2页浏览型号CY62126EV30LL-45ZSXIT的Datasheet PDF文件第3页浏览型号CY62126EV30LL-45ZSXIT的Datasheet PDF文件第4页浏览型号CY62126EV30LL-45ZSXIT的Datasheet PDF文件第5页浏览型号CY62126EV30LL-45ZSXIT的Datasheet PDF文件第6页浏览型号CY62126EV30LL-45ZSXIT的Datasheet PDF文件第7页 
CY62126EV30 MoBL  
1-Mbit (64K x 16) Static RAM  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life(MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption when addresses are not toggling. Placing the  
device in standby mode reduces power consumption by more  
than 99 percent when deselected (CE HIGH). The input and  
output pins (I/O0 through I/O15) are placed in a high impedance  
state when the device is deselected (CE HIGH), the outputs are  
disabled (OE HIGH), both Byte High Enable and Byte Low  
Enable are disabled (BHE, BLE HIGH) or during a write  
operation (CE LOW and WE LOW).  
Features  
■ High speed: 45 ns  
■ Temperature ranges  
❐ Industrial: –40 °C to +85 °C  
❐ Automotive: –40 °C to +125 °C  
■ Wide voltage range: 2.2 V to 3.6 V  
■ Pin compatible with CY62126DV30  
■ Ultra low standby power  
❐ Typical standby current: 1 A  
❐ Maximum standby current: 4 A  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7) is written into the location  
specified on the address pins (A0 through A15). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A15).  
■ Ultra low active power  
❐ Typical active current: 1.3 mA at f = 1 MHz  
■ Easy memory expansion with CE and OE features  
■ Automatic power down when deselected  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appear on I/O0 to I/O7. If  
Byte High Enable (BHE) is LOW, then data from memory  
appears on I/O8 to I/O15. See the “Truth Table” on page 11 for a  
complete description of read and write modes.  
■ Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
■ OfferedinPb-free48-ballveryfinepitchballgridarray(VFBGA)  
and 44-pin thin small outline package (TSOP) II packages  
Functional Description  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
The CY62126EV30 is a high performance CMOS static RAM  
organized as 64K words by 16 bits. This device features  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
64K x 16  
I/O0–I/O7  
RAM Array  
I/O8–I/O15  
A2  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
Document #: 38-05486 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised December 17, 2010  
1234567...16

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CY62126EV30LL-45ZSXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY62126EV30LL-45ZSXI CYPRESS

类似代替

 1-Mbit (64K x 16) Static RAM
IS62WV6416BLL-55TLI ISSI

功能相似

 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

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