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CY62127BVLL-55ZI PDF预览

CY62127BVLL-55ZI

更新时间： 2024-09-14 22:15:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 267K
描述
64K x 16 Static RAM

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中文翻译

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CY62127BVLL-55ZI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSOP2包装说明：TSOP2, TSOP44,.46,32
针数：44Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.8最长访问时间：55 ns
I/O 类型：COMMONJESD-30 代码：R-PDSO-G44
JESD-609代码：e0长度：18.415 mm
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：44
字数：65536 words字数代码：64000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64KX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP2封装等效代码：TSOP44,.46,32
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：3/3.3 V认证状态：Not Qualified
座面最大高度：1.194 mm最大待机电流：0.000015 A
最小待机电流：2 V子类别：SRAMs
最大压摆率：0.02 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：10.16 mm

CY62127BVLL-55ZI 数据手册

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27BV  
CY62127BV  
64K x 16 Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is  
written into the location specified on the address pins (A0  
through A15). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O9 through I/O16) is written into the location  
specified on the address pins (A0 through A15).  
Features  
• 2.7V–3.6V operation  
• CMOS for optimum speed/power  
• Low active power (70 ns, LL version)  
— 54 mW (max.) (15 mA)  
• Low standby power (70 ns, LL version)  
— 54 µW (max.) (15 µA)  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O9 to I/O16. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Automatic power-down when deselected  
— Power down either with CE or BHE and BLE HIGH  
• Independent control of Upper and Lower Bytes  
• Available in 44-pin TSOP II (forward) and fBGA  
Functional Description  
The input/output pins (I/O1 through I/O16) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
The CY62127BV is a high-performance CMOS Static RAM  
organized as 65,536 words by 16 bits. This device has an au-  
tomatic power-down feature that significantly reduces power  
consumption by 99% when deselected. The device enters  
power-down mode when CE is HIGH or when CE is LOW and  
both BLE and BHE are HIGH.  
The CY62127BV is available in standard 44-pin TSOP Type II  
(forward pinout) and fBGA packages.  
Logic Block Diagram  
Pin  
Configurations  
TSOP II (Forward)  
Top View  
DATA IN DRIVERS  
44  
1
A
4
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
A
A
A
A
A
A
A
A
A
12  
11  
10  
A
A
2
7
OE  
A
1
A
BHE  
BLE  
I/O  
I/O  
I/O  
0
9
7
6
CE  
64K x 16  
I/O  
7
1
16  
I/O –I/O  
RAM Array  
1024 X 1024  
37  
36  
35  
34  
33  
1
8
I/O  
I/O  
8
2
3
15  
14  
13  
3
2
9
I/O –I/O  
10  
11  
12  
13  
9
16  
I/O  
V
SS  
I/O  
4
CC  
V
SS  
1
0
V
V
CC  
A
I/O  
32  
31  
30  
29  
28  
27  
I/O  
I/O  
5
6
7
8
12  
11  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
I/O  
10  
9
COLUMN DECODER  
WE 17  
18  
NC  
A
A
A
A
15  
14  
13  
8
19  
20  
21  
22  
26  
25  
A
9
10  
11  
A
A
BHE  
A
12  
WE  
CE  
OE  
24  
23  
NC  
NC  
BLE  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05155 Rev. **  
Revised September 6, 2001  
1234567...11

中文翻译

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