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CY62126EV30LL-55ZSXET PDF预览

CY62126EV30LL-55ZSXET

更新时间: 2024-11-05 20:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
16页 300K
描述
Standard SRAM, 64KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

CY62126EV30LL-55ZSXET 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active包装说明:TSOP2, TSOP44,.46,32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.32.00.41风险等级:5.56
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44JESD-609代码:e4
长度:18.415 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:44字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-40 °C
组织:64KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:2.5/3.3 V
认证状态:Not Qualified座面最大高度:1.194 mm
最大待机电流:0.00003 A最小待机电流:1.5 V
子类别:SRAMs最大压摆率:0.035 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:10.16 mm
Base Number Matches:1

CY62126EV30LL-55ZSXET 数据手册

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CY62126EV30 MoBL  
1-Mbit (64K x 16) Static RAM  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life(MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption when addresses are not toggling. Placing the  
device in standby mode reduces power consumption by more  
than 99 percent when deselected (CE HIGH). The input and  
output pins (I/O0 through I/O15) are placed in a high impedance  
state when the device is deselected (CE HIGH), the outputs are  
disabled (OE HIGH), both Byte High Enable and Byte Low  
Enable are disabled (BHE, BLE HIGH) or during a write  
operation (CE LOW and WE LOW).  
Features  
High speed: 45 ns  
Temperature ranges  
Industrial: –40 °C to +85 °C  
Automotive: –40 °C to +125 °C  
Wide voltage range: 2.2 V to 3.6 V  
Pin compatible with CY62126DV30  
Ultra low standby power  
Typical standby current: 1 A  
Maximum standby current: 4 A  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7) is written into the location  
specified on the address pins (A0 through A15). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A15).  
Ultra low active power  
Typical active current: 1.3 mA at f = 1 MHz  
Easy memory expansion with CE and OE features  
Automatic power down when deselected  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appear on I/O0 to I/O7. If  
Byte High Enable (BHE) is LOW, then data from memory  
appears on I/O8 to I/O15. See the “Truth Table” on page 11 for a  
complete description of read and write modes.  
Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
OfferedinPb-free48-ballveryfinepitchballgridarray(VFBGA)  
and 44-pin thin small outline package (TSOP) II packages  
Functional Description  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
The CY62126EV30 is a high performance CMOS static RAM  
organized as 64K words by 16 bits. This device features  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
64K x 16  
I/O0–I/O7  
RAM Array  
I/O8–I/O15  
A2  
A1  
A0  
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
Cypress Semiconductor Corporation  
Document #: 38-05486 Rev. *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised December 17, 2010  

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