Datasheet > CY62126EV30_09

CY62126EV30_09

更新时间： 2024-09-13 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	460K
描述
1-Mbit (64K x 16) Static RAM

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CY62126EV30_09 数据手册

MoBL^®,CY62126EV30

1-Mbit (64K x 16) Static RAM

Features

Functional Description

■ High speed: 45 ns

The CY62126EV30 is a high performance CMOS static RAM

organized as 64K words by 16 bits^[1]. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^®) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

consumption when addresses are not toggling. Placing the

device in standby mode reduces power consumption by more

than 99 percent when deselected (CE HIGH). The input and

output pins (IO₀through IO₁₅) are placed in a high impedance

state when:

■ Temperature ranges

❐ Industrial: –40°C to +85°C

❐ Automotive: –40°C to +125°C

■ Wide voltage range: 2.2V to 3.6V

■ Pin compatible with CY62126DV30

■ Ultra low standby power

❐ Typical standby current: 1 μA

❐ Maximum standby current: 4 μA

■ Deselected (CE HIGH)

■ Ultra low active power

❐ Typical active current: 1.3 mA at f = 1 MHz

■ Outputs are disabled (OE HIGH)

■ Both Byte High Enable and Byte Low Enable are disabled

(BHE, BLE HIGH)

■ Easy memory expansion with CE and OE features

■ Automatic power down when deselected

■ CMOS for optimum speed and power

■ Write operation is active (CE LOW and WE LOW)

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from IO pins (IO₀through IO₇) is written into the location

specified on the address pins (A₀through A₁₅). If Byte High

■ Offered in Pb-free 48-ball VFBGA and 44-pin TSOP II

packages

Enable (BHE) is LOW, then data from IO pins (IO₈through IO₁₅

)

is written into the location specified on the address pins (A₀

through A₁₅).

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appear on IO₀to IO₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on IO₈to IO₁₅. See the “Truth Table” on page 9 for a

complete description of read and write modes.

Logic Block Diagram

Note

1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.

Cypress Semiconductor Corporation

Document #: 38-05486 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 5, 2009

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与CY62126EV30_09相关器件

型号	品牌	获取价格	描述	数据表
CY62126EV30_10	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30_11	CYPRESS	获取价格	1-Mbit (64 K x 16) Static RAM Automatic power down when deselected
CY62126EV30LL	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30LL-45BVXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30LL-45BVXI	INFINEON	获取价格	Asynchronous SRAM
CY62126EV30LL-45BVXIT	CYPRESS	获取价格	Standard SRAM, 64KX16, 45ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY62126EV30LL-45BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY62126EV30LL-45ZSXA	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30LL-45ZSXA	INFINEON	获取价格	Asynchronous SRAM
CY62126EV30LL-45ZSXAT	CYPRESS	获取价格	Standard SRAM, 64KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44

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