Datasheet > CY62126ESL

CY62126ESL

更新时间： 2024-09-13 09:42:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
12页	408K
描述
1-Mbit (64K x 16) Static RAM

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CY62126ESL 数据手册

CY62126ESL MoBL^®

1-Mbit (64K x 16) Static RAM

consumption when addresses are not toggling. Placing the

device into standby mode reduces power consumption by more

than 99 percent when deselected (CE HIGH). The input and

output pins (IO₀through IO₁₅) are placed in a high impedance

state when the device is deselected (CE HIGH), the outputs are

disabled (OE HIGH), both Byte High Enable and Byte Low

Enable are disabled (BHE, BLE HIGH) or during a write

operation (CE LOW and WE LOW).

Features

■ Very high speed: 45 ns

■ Wide voltage range: 2.2V–3.6V and 4.5V–5.5V

■ Ultra low standby power

❐ Typical standby current: 1 μA

❐ Maximum standby current: 4 μA

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data

from IO pins (IO₀through IO₇) is written into the location

specified on the address pins (A₀through A₁₅). If Byte High

■ Ultra low active power

❐ Typical active current: 1.3 mA at f = 1 MHz

■ Easy memory expansion with CE, and OE features

■ Automatic power down when deselected

■ CMOS for optimum speed and power

Enable (BHE) is LOW, then data from IO pins (IO₈through IO₁₅

)

is written into the location specified on the address pins (A₀

through A₁₅).

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If

Byte Low Enable (BLE) is LOW, then data from the memory

location specified by the address pins appear on IO₀to IO₇. If

Byte High Enable (BHE) is LOW, then data from memory

appears on IO₈to IO₁₅. See the Truth Table on page 10 for a

complete description of read and write modes.

■ Available in Pb-free 44-Pin TSOP II package

Functional Description

The CY62126ESL is a high performance CMOS static RAM

organized as 64K words by 16 bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^®) in portable

applications such as cellular telephones. The device also has an

automatic power down feature that significantly reduces power

For best practice recommendations, refer to the Cypress

application note AN1064, SRAM System Guidelines.

Logic Block Diagram

DATA IN DRIVERS

A₁₀

A₉

A₈

A₇

A₆

A₅

A₄

A₃

64K x 16

IO₀–IO₇

RAM Array

IO₈–IO₁₅

A₂

A₁

A₀

COLUMN DECODER

BHE

BLE

Cypress Semiconductor Corporation

Document #: 001-45076 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 15, 2009

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与CY62126ESL相关器件

型号	品牌	获取价格	描述	数据表
CY62126ESL_13	CYPRESS	获取价格	1-Mbit (64 K x 16) Static RAM
CY62126ESL-45ZSXA	CYPRESS	获取价格	Standard SRAM, 64KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62126ESL-45ZSXAT	CYPRESS	获取价格	Standard SRAM, 64KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62126ESL-45ZSXI	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126ESL-45ZSXIT	CYPRESS	获取价格	Standard SRAM, 64KX16, 45ns, CMOS, PDSO44, LEAD FREE, TSSOP2-44
CY62126EV30	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30_09	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30_10	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM
CY62126EV30_11	CYPRESS	获取价格	1-Mbit (64 K x 16) Static RAM Automatic power down when deselected
CY62126EV30LL	CYPRESS	获取价格	1-Mbit (64K x 16) Static RAM

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