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CDCM9102RHBT PDF预览

CDCM9102RHBT

更新时间: 2024-09-15 11:46:03
品牌 Logo 应用领域
德州仪器 - TI 晶体时钟发生器微控制器和处理器外围集成电路
页数 文件大小 规格书
22页 766K
描述
Low-Noise Two-Channel 100-MHz Clock Generator

CDCM9102RHBT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active包装说明:VQFN-32
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.04Is Samacsys:N
JESD-30 代码:S-PQCC-N32JESD-609代码:e4
长度:5 mm湿度敏感等级:2
端子数量:32最高工作温度:85 °C
最低工作温度:-40 °C最大输出时钟频率:100 MHz
封装主体材料:PLASTIC/EPOXY封装代码:HVQCCN
封装等效代码:LCC32,.2SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:3.3 V主时钟/晶体标称频率:25 MHz
认证状态:Not Qualified座面最大高度:1 mm
子类别:Clock Generators最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

CDCM9102RHBT 数据手册

 浏览型号CDCM9102RHBT的Datasheet PDF文件第2页浏览型号CDCM9102RHBT的Datasheet PDF文件第3页浏览型号CDCM9102RHBT的Datasheet PDF文件第4页浏览型号CDCM9102RHBT的Datasheet PDF文件第5页浏览型号CDCM9102RHBT的Datasheet PDF文件第6页浏览型号CDCM9102RHBT的Datasheet PDF文件第7页 
CDCM9102  
www.ti.com  
SCAS922 FEBRUARY 2012  
Low-Noise Two-Channel 100-MHz Clock Generator  
Check for Samples: CDCM9102  
1
FEATURES  
2
Integrated Low-Noise Clock Generator  
Including PLL, VCO, and Loop Filter  
Output Enable Pin Shuts Off Device and  
Outputs.  
Two Low-Noise 100-MHz Clocks (LVPECL,  
LVDS, or pair of LVCMOS)  
5-mm × 5-mm QFN-32 Package  
ESD Protection Exceeds 2 kV HBM, 500 V CDM  
Industrial Temperature Range (40°C to 85°C)  
3.3-V Power Supply  
Support for HCSL Signaling Levels  
(AC-Coupled)  
Typical Period Jitter: 21 ps pk-pk  
Typical Random Jitter: 510 fs  
Output Type Set by Pins  
APPLICATIONS  
Reference Clock Generation for PCI Express  
Gen 1, Gen2, and Gen3  
Bonus Single-ended 25-MHz Output  
General-Purpose Clocking  
Integrated Crystal Oscillator Input Accepts  
25-MHz Crystal  
DESCRIPTION  
The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communications  
standards such as PCI Express. The device is easy to configure and use. The CDCM9102 provides two  
100-MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of  
LVCMOS buffers. HCSL signaling is supported using an ac-coupled network. The user configures the output  
buffer type desired by strapping device pins. Additionally, a single-ended 25-MHz clock output port is provided.  
Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for  
additional clock generators. All clocks generated are derived from a single external 25-MHz crystal.  
25 MHz  
Low  
Noise  
PCIe 100 MHz  
XO  
Clock  
25 MHz  
100 MHz  
PCIe  
Generator  
CDCM9102  
Figure 1. CDCM9102 Typical Application Example  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PCI Express is a trademark of PCI-SIG .  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2012, Texas Instruments Incorporated  

CDCM9102RHBT 替代型号

型号 品牌 替代类型 描述 数据表
CDCM9102RHBR TI

完全替代

Low-Noise Two-Channel 100-MHz Clock Generator
SI52143-A01AGM SILICON

功能相似

Clock Generator, 100MHz, CMOS, 4 X 4 MM, MO-220VGGD-8, QFN-20

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