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CDCR83DBQRG4 PDF预览

CDCR83DBQRG4

更新时间： 2024-11-18 14:41:23
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
16页 500K
描述
400MHz Direct Rambus ™ Clock Generator 24-SSOP -40 to 85

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中文翻译

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CDCR83DBQRG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SSOP,
针数：24Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.77系列：83
输入调节：STANDARDJESD-30 代码：R-PDSO-G24
JESD-609代码：e4长度：8.65 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER湿度敏感等级：2
功能数量：1反相输出次数：
端子数量：24实输出次数：1
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.75 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
最小 fmax：400 MHzBase Number Matches：1

CDCR83DBQRG4 数据手册

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SCAS632B − APRIL 2001 − REVISED OCTOBER 2005  
D
D
D
400-MHz Differential Clock Source for  
Direct Rambus Memory Systems for an  
800-MHz Data Transfer Rate  
D
D
D
Cycle-Cycle Jitter Is Less Than 50 ps at  
400 MHz  
Certified by Gigatest Labs to Exceed the  
Rambus DRCG Validation Requirement  
Synchronizes the Clock Domains of the  
Rambus Channel With an External System  
or Processor Clock  
Supports Industrial Temperature Range of  
°
°
−40 C to 85 C  
Three Power Operating Modes to Minimize  
Power for Mobile and Other  
Power-Sensitive Applications  
DBQ PACKAGE  
(TOP VIEW)  
V
IR  
S0  
S1  
V
D
D
D
D
D
D
Operates From a Single 3.3-V Supply and  
120 mW at 300 MHz (Typ)  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
DD  
REFCLK  
2
V
P
O
3
Packaged in a Shrink Small-Outline  
Package (DBQ)  
DD  
DD  
GNDP  
GNDI  
GNDO  
CLK  
4
5
Supports Frequency Multipliers: 4, 6, 8,  
16/3  
PCLKM  
SYNCLKN  
GNDC  
NC  
6
CLKB  
GNDO  
7
No External Components Required for PLL  
Supports Independent Channel Clocking  
8
V
C
V
O
9
DD  
DD  
Spread Spectrum Clocking Tracking  
Capability to Reduce EMI  
V
IPD  
MULT0  
MULT1  
10  
11  
DD  
STOPB  
D
Designed for Use With TI’s 133-MHz Clock  
Synthesizers CDC924 and CDC921  
PWRDNB 12  
13 S2  
NC − No internal connection  
description  
The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus  
memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system  
or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and  
mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus  
memory applications.  
The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to  
enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct  
Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the  
DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK  
to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK  
frequencies by ratios M and N such that PCLKM = SYNCLKN, where SYNCLK = BUSCLK/4. The DRCG detects  
the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew  
between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK  
boundary without incurring additional latency.  
User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of  
one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 400 MHz  
with clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a  
bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for  
systems where synchronization between the Rambus clock and a system clock is not required. Test modes are  
provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a  
high-impedance state for board testing.  
The CDCR83 is characterized for operation over free-air temperatures of −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Direct Rambus and Rambus are trademarks of Rambus Inc.  
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Copyright 2001 − 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

中文翻译

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CDCR83DBQRG4 替代型号

型号 品牌 替代类型 描述 数据表
CDCR83DBQG4 TI

完全替代

 400MHz Direct Rambus ™ Clock Generator 24-SSOP -40 to 85
CDCR83DBQR TI

完全替代

 400MHz Direct Rambus ™ Clock Generator 24-SSOP -40 to 85
CDCR83DBQ TI

完全替代

 DIRECT RAMBUS CLOCK GENERATOR

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