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CDCU2A877ZQL

更新时间： 2024-11-06 03:29:03
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器
页数 文件大小 规格书
14页 370K
描述
1.8-V PHASE LOCK LOOP CLOCK DRIVER

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CDCU2A877ZQL 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：VFBGA,针数：52
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.77系列：877
输入调节：DIFFERENTIALJESD-30 代码：R-PBGA-B52
JESD-609代码：e1长度：7 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER功能数量：1
反相输出次数：端子数量：52
实输出次数：10最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.035 ns
座面最大高度：1 mm最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES温度等级：COMMERCIAL
端子面层：TIN SILVER COPPER端子形式：BALL
端子节距：0.65 mm端子位置：BOTTOM
宽度：4.5 mm最小 fmax：410 MHz
Base Number Matches：1

CDCU2A877ZQL 数据手册

 浏览型号CDCU2A877ZQL的Datasheet PDF文件第2页浏览型号CDCU2A877ZQL的Datasheet PDF文件第3页浏览型号CDCU2A877ZQL的Datasheet PDF文件第4页浏览型号CDCU2A877ZQL的Datasheet PDF文件第5页浏览型号CDCU2A877ZQL的Datasheet PDF文件第6页浏览型号CDCU2A877ZQL的Datasheet PDF文件第7页 
CDCU2A877  
www.ti.com  
SCAS827–AUGUST 2006  
1.8-V PHASE LOCK LOOP CLOCK DRIVER  
FEATURES  
•
•
High-Drive Version of CDCUA877  
52-Ball mBGA (MicroStar Junior™ BGA,  
0,65-mm pitch)  
•
1.8-V/1.9-V Phase Lock Loop Clock Driver for  
Double Data Rate ( DDR II ) Applications  
•
•
•
•
•
•
•
Spread Spectrum Clock Compatible  
Operating Frequency: 125 MHz to 410 MHz  
Application Frequency: 160 MHz to 410 MHz  
Low Jitter (Cycle-Cycle): ±40 ps  
Low Output Skew: 35 ps  
•
•
•
External Feedback Pins ( FBIN, FBIN ) are  
Used to Synchronize the Outputs to the Input  
Clocks  
Meets or Exceeds CUA877/CUA878  
Specification PLL Standard for  
PC2-3200/4300/5300/6400  
Stabilization Time <6 µs  
Fail-Safe Inputs  
Distributes One Differential Clock Input to 10  
Differential Outputs  
DESCRIPTION  
The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock  
input pair (CK, CK) to 10 differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock  
outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks  
(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the  
clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in  
frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions  
as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.  
When AVDD is grounded, the PLL is turned off and bypassed for test purposes.  
When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection  
circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low  
power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being  
logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the  
PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within  
the specified stabilization time.  
The CDCU2A877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from  
0°C to 70°C.  
AVAILABLE OPTIONS  
TA  
52-Ball BGA(1)  
0°C to 70°C  
CDCU2A877ZQL  
(1) For the most current package and ordering information, see the  
Package Option Addendum at the end of this document, or see the  
TI website at www.ti.com.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
MicroStar Junior is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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