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CDCU877AGQLR PDF预览

CDCU877AGQLR

更新时间： 2024-11-18 19:57:55
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
16页 326K
描述
IC 877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52, 0.65 MM PITCH, PLASTIC, BGA-52, Clock Driver

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CDCU877AGQLR 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：VFBGA, BGA52,6X10,25
针数：52Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：7.84系列：877
输入调节：DIFFERENTIALJESD-30 代码：R-PBGA-B52
长度：7 mm逻辑集成电路类型：PLL BASED CLOCK DRIVER
最大I（ol）：0.009 A功能数量：1
反相输出次数：端子数量：52
实输出次数：10最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：VFBGA
封装等效代码：BGA52,6X10,25封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.8 V认证状态：Not Qualified
Same Edge Skew-Max（tskwd）：0.035 ns座面最大高度：1 mm
子类别：Clock Drivers最大供电电压 (Vsup)：1.9 V
最小供电电压 (Vsup)：1.7 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.65 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.5 mm
最小 fmax：340 MHzBase Number Matches：1

CDCU877AGQLR 数据手册

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SCAS688A − JUNE 2003 − REVISED JANUARY 2004  
D
1.8-V Phase Lock Loop Clock Driver for  
Double Data Rate (DDR II) Applications  
D
External Feedback Pins (FBIN, FBIN) are  
Used to Synchronize the Outputs to the  
Input Clocks  
D
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Spread Spectrum Clock Compatible  
Operating Frequency: 10 MHz to 400 MHz  
Low Current Consumption: <135 mA  
Low Jitter (Cycle-Cycle): 30 ps  
Low Output Skew: 35 ps  
D
D
D
Single-Ended Input and Single-Ended  
Output Modes  
Meets or Exceeds JESD82-8 PLL Standard  
for PC2-3200/4300  
Fail-Safe Inputs  
Low Period Jitter: 20 ps  
Low Dynamic Phase Offset:: 15 ps  
Low Static Phase Offset:: 50 ps  
Distributes One Differential Clock Input to  
Ten Differential Outputs  
D
52-Ball µBGA (MicroStar JuniorBGA,  
0,65-mm pitch) and 40-Pin MLF  
description  
The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input  
pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs  
(FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN),  
the LVCMOS control pins (OE, OS), and the analog power input (AV ). When OE is low, the clock outputs, except  
DD  
FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select)  
is a program pin that must be tied to GND or V . When OS is high, OE functions as previously described. When  
DD  
OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AV  
off and bypassed for test purposes.  
is grounded, the PLL is turned  
DD  
When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit  
on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state  
where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being  
differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock  
between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.  
The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from –40°C  
to 85°C.  
AVAILABLE OPTIONS  
T
A
52-Ball BGA  
40-Pin MLF  
CDCU877ZQL  
(Pb-Free)  
−40°C to 85°C  
−40°C to 85°C  
CDCU877RTB  
CDCU877AZQL  
(Pb-Free)  
CDCU877ARTB  
−40°C to 85°C  
−40°C to 85°C  
CDCU877GQL  
CDCU877AGQL  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
MicroStar Junior is a trademark of Texas Instruments.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

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