5秒后页面跳转
捷配首页

Datasheet > CDCU877ARTBR
CDCU877ARTBR PDF预览

CDCU877ARTBR

更新时间： 2024-11-18 19:57:55
品牌 Logo 应用领域
德州仪器 - TI 驱动动态存储器双倍数据速率逻辑集成电路
页数 文件大小 规格书
16页 326K
描述
1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 40-VQFN -40 to 85

阅读下载

中文翻译

获取价格

CDCU877ARTBR 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC40,.24SQ,20针数：40
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.16
系列：877输入调节：DIFFERENTIAL
JESD-30 代码：S-PQCC-N40长度：6 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.009 A
功能数量：1反相输出次数：
端子数量：40实输出次数：10
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC40,.24SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.8 V
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.035 ns
座面最大高度：0.9 mm子类别：Clock Drivers
最大供电电压 (Vsup)：1.9 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6 mm最小 fmax：340 MHz
Base Number Matches：1

CDCU877ARTBR 数据手册

 浏览型号CDCU877ARTBR的Datasheet PDF文件第2页浏览型号CDCU877ARTBR的Datasheet PDF文件第3页浏览型号CDCU877ARTBR的Datasheet PDF文件第4页浏览型号CDCU877ARTBR的Datasheet PDF文件第5页浏览型号CDCU877ARTBR的Datasheet PDF文件第6页浏览型号CDCU877ARTBR的Datasheet PDF文件第7页 
ꢀꢁꢀ ꢂꢃ ꢄ ꢄ ꢅꢀ ꢁꢀ ꢂꢃ ꢄꢄ ꢆ  
ꢇ ꢈꢃ ꢉꢊ ꢋꢌ ꢆꢍꢎ ꢏ ꢐ ꢀꢑ ꢏ ꢐꢐ ꢋ ꢀꢏ ꢐ ꢀꢑ ꢁ ꢒꢓ ꢊ ꢎꢒ  
ꢔ
SCAS688A − JUNE 2003 − REVISED JANUARY 2004  
D
1.8-V Phase Lock Loop Clock Driver for  
Double Data Rate (DDR II) Applications  
D
External Feedback Pins (FBIN, FBIN) are  
Used to Synchronize the Outputs to the  
Input Clocks  
D
D
D
D
D
D
D
D
D
Spread Spectrum Clock Compatible  
Operating Frequency: 10 MHz to 400 MHz  
Low Current Consumption: <135 mA  
Low Jitter (Cycle-Cycle): 30 ps  
Low Output Skew: 35 ps  
D
D
D
Single-Ended Input and Single-Ended  
Output Modes  
Meets or Exceeds JESD82-8 PLL Standard  
for PC2-3200/4300  
Fail-Safe Inputs  
Low Period Jitter: 20 ps  
Low Dynamic Phase Offset:: 15 ps  
Low Static Phase Offset:: 50 ps  
Distributes One Differential Clock Input to  
Ten Differential Outputs  
D
52-Ball µBGA (MicroStar JuniorBGA,  
0,65-mm pitch) and 40-Pin MLF  
description  
The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input  
pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs  
(FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks (FBIN, FBIN),  
the LVCMOS control pins (OE, OS), and the analog power input (AV ). When OE is low, the clock outputs, except  
DD  
FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select)  
is a program pin that must be tied to GND or V . When OS is high, OE functions as previously described. When  
DD  
OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AV  
off and bypassed for test purposes.  
is grounded, the PLL is turned  
DD  
When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection circuit  
on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state  
where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being  
differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock  
between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.  
The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from –40°C  
to 85°C.  
AVAILABLE OPTIONS  
T
A
52-Ball BGA  
40-Pin MLF  
CDCU877ZQL  
(Pb-Free)  
−40°C to 85°C  
−40°C to 85°C  
CDCU877RTB  
CDCU877AZQL  
(Pb-Free)  
CDCU877ARTB  
−40°C to 85°C  
−40°C to 85°C  
CDCU877GQL  
CDCU877AGQL  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
MicroStar Junior is a trademark of Texas Instruments.  
ꢋ
ꢋ
ꢒ
ꢐ
ꢦ
ꢁ
ꢡ
ꢂ
ꢀ
ꢟ
ꢕ
ꢠ
ꢓ
ꢚ
ꢐ
ꢘ
ꢖ
ꢙ
ꢁ
ꢆ
ꢕ
ꢆ
ꢗ
ꢘ
ꢢ
ꢙ
ꢚ
ꢠ
ꢛ
ꢜ
ꢝ
ꢝ
ꢞ
ꢞ
ꢗ
ꢗ
ꢚ
ꢚ
ꢘ
ꢘ
ꢗ
ꢟ
ꢟ
ꢣ
ꢠ
ꢡ
ꢛ
ꢛ
ꢢ
ꢢ
ꢘ
ꢞ
ꢝ
ꢜ
ꢟ
ꢟ
ꢚ
ꢙ
ꢣ
ꢕꢢ  
ꢡ
ꢤ
ꢟ
ꢥ
ꢗ
ꢠ
ꢝ
ꢟ
ꢞ
ꢗ
ꢞ
ꢚ
ꢛ
ꢘ
ꢡ
ꢦ
ꢝ
ꢘ
ꢞ
ꢞ
ꢢ
ꢟ
ꢈ
Copyright 2004, Texas Instruments Incorporated  
ꢛ
ꢚ
ꢠ
ꢞ
ꢚ
ꢛ
ꢜ
ꢞ
ꢚ
ꢟ
ꢣ
ꢗ
ꢙ
ꢗ
ꢠ
ꢢ
ꢛ
ꢞ
ꢧ
ꢞ
ꢢ
ꢛ
ꢚ
ꢙ
ꢨ
ꢝ
ꢓ
ꢘ
ꢜ
ꢢ
ꢟ
ꢞ
ꢝ
ꢘ
ꢦ
ꢝ
ꢛ
ꢦ
ꢩ
ꢝ
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢫ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢈ  
ꢛ
ꢛ
ꢝ
ꢘ
ꢞ
ꢪ
ꢈ
ꢋ
ꢛ
ꢚ
ꢦ
ꢡ
ꢠ
ꢞ
ꢗ
ꢚ
ꢘ
ꢣ
ꢛ
ꢚ
ꢠ
ꢢ
ꢟ
ꢟ
ꢗ
ꢘ
ꢫ
ꢦ
ꢚ
ꢢ
ꢟ
ꢘ
ꢚ
ꢞ
ꢘ
ꢢ
ꢠ
ꢢ
ꢟ
ꢟ
ꢝ
ꢛ
ꢗ
ꢥ
ꢪ
ꢗ
ꢘ
ꢠ
ꢥ
ꢡ
ꢦ
ꢢ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

中文翻译

下载PDF

与CDCU877ARTBR相关器件

型号 品牌 获取价格 描述 数据表
CDCU877ARTBT TI

获取价格

 		877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40, 6 X 6
CDCU877AZQL TI

获取价格

 		1.8V PHASE LOCK LOOP CLOCK DRIVER
CDCU877AZQLR TI

获取价格

 		暂无描述
CDCU877AZQLT TI

获取价格

 		暂无描述
CDCU877B SEME-LAB

获取价格

 		1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU877BZQLR TI

获取价格

 		1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 52-BGA MICROSTAR JUNIOR -40
CDCU877GQL TI

获取价格

 		1.8V PHASE LOCK LOOP CLOCK DRIVER
CDCU877GQLR TI

获取价格

 		1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 52-BGA MICROSTAR JUNIOR -40
CDCU877RHA TI

获取价格

 		1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU877RHAR TI

获取价格

 		适用于 DDR2 SDRAM 应用的 1.8V 锁相环路时钟驱动器 | RHA | 40

与CDCU877ARTBR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证