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CDCUA877 PDF预览

CDCUA877

更新时间: 2024-11-09 03:29:03
品牌 Logo 应用领域
德州仪器 - TI 时钟驱动器
页数 文件大小 规格书
16页 579K
描述
1.8-V PHASE LOCK LOOP CLOCK DRIVER

CDCUA877 数据手册

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CDCUA877  
www.ti.com  
SCAS769AAUGUST 2006REVISED JUNE 2007  
1.8-V PHASE LOCK LOOP CLOCK DRIVER  
FEATURES  
Distributes One Differential Clock Input to Ten  
Differential Outputs  
1.8-V/1.9-V Phase Lock Loop Clock Driver for  
Double Data Rate (DDR II) Applications  
52-Ball μBGA (MicroStar Junior™ BGA,  
0,65-mm pitch)  
Spread Spectrum Clock Compatible  
Operating Frequency: 125 MHz to 410 MHz  
Application Frequency: 160 MHz to 410 MHz  
Low Current Consumption: <200 mA Typ  
Low Jitter (Cycle-Cycle): ±40 ps  
Low Output Skew: 35 ps  
External Feedback Pins (FBIN, FBIN) are Used  
to Synchronize the Outputs to the Input  
Clockst  
Meets or Exceeds CUA877/CAU878  
Specification PLL Standard for  
PC2-3200/4300/5300/6400o  
Stabilization Time <6 μs  
Fail-Safe Inputs  
DESCRIPTION  
The CDCUA877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock  
input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock  
outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks  
(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the  
clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in  
frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions  
as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.  
When AVDD is grounded, the PLL is turned off and bypassed for test purposes.  
When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection  
circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low  
power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being  
logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the  
PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within  
the specified stabilization time.  
The CDCUA877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from  
–40°C to 85°C).  
AVAILABLE OPTIONS  
TA  
52-Ball BGA(1)  
–40°C to 85°C  
CDCUA877ZQL  
(1) For the most current package and ordering information, see the  
Package Option Addendum at the end of this document, or see the  
TI website at www.ti.com.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
MicroStar Junior is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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