CDCU877AZQLR

更新时间： 2024-11-06 13:06:43

品牌	Logo	应用领域
德州仪器 - TI		时钟驱动器
页数	文件大小	规格书
23页	945K
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CDCU877AZQLR 数据手册

CDCU877, CDCU877A

1.8-V PHASE LOCK LOOP CLOCK DRIVER

www.ti.com

SCAS688D–JUNE 2005–REVISED JULY 2007

FEATURES

•

Low Static Phase Offset: ±50 ps

•

1.8-V Phase Lock Loop Clock Driver for

Double Data Rate (DDR II) Applications

Distributes One Differential Clock Input to Ten

Differential Outputs

•

Spread Spectrum Clock Compatible

Operating Frequency: 10 MHz to 400 MHz

Low Current Consumption: <135 mA

Low Jitter (Cycle-Cycle): ±30 ps

Low Output Skew: 35 ps

•

52-Ball μBGA (MicroStar™ Junior BGA,

0,65-mm pitch) and 40-Pin MLF

External Feedback Pins (FBIN, FBIN) are Used

to Synchronize the Outputs to the Input

Clocks

•

Meets or Exceeds JESD82-8 PLL Standard for

PC2-3200/4300

Low Period Jitter: ±20 ps

Low Dynamic Phase Offset: ±15 ps

Fail-Safe Inputs

DESCRIPTION

The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock

input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock

outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks

(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AV_DD). When OE is low, the

clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in

frequency. OS (output select) is a program pin that must be tied to GND or V_DD. When OS is high, OE functions

as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.

When AV_DDis grounded, the PLL is turned off and bypassed for test purposes.

When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection

circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low

power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being

logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the

PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within

the specified stabilization time.

The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from

—40°C to 85°C.

ORDERING INFORMATION

(1)

T_A

52-BALL BGA

CDCU877ZQL

CDCU877AZQL

CDCU877GQL

CDCU877AGQL

40-Pin MLF

CDCU877RHA

CDCU877ARHA

CDCU877RTB

CDCU877ARTB

-40°C to 85°C

(1) For the most current package and ordering information, see the

Package Option Addendum at the end of this document, or see the

TI website at www.ti.com.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...23

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CDCU877AZQLR 替代型号

型号	品牌	替代类型	描述	数据表
CDCU877AZQLT	TI	完全替代	暂无描述
CDCU877ARHAT	TI	类似代替	1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 40-VQFN -40 to 85

与CDCU877AZQLR相关器件

型号	品牌	获取价格	描述	数据表
CDCU877AZQLT	TI	获取价格	暂无描述
CDCU877B	SEME-LAB	获取价格	1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU877BZQLR	TI	获取价格	1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 52-BGA MICROSTAR JUNIOR -40
CDCU877GQL	TI	获取价格	1.8V PHASE LOCK LOOP CLOCK DRIVER
CDCU877GQLR	TI	获取价格	1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 52-BGA MICROSTAR JUNIOR -40
CDCU877RHA	TI	获取价格	1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU877RHAR	TI	获取价格	适用于 DDR2 SDRAM 应用的 1.8V 锁相环路时钟驱动器 \| RHA \| 40
CDCU877RHARG4	TI	获取价格	1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU877RHAT	TI	获取价格	适用于 DDR2 SDRAM 应用的 1.8V 锁相环路时钟驱动器 \| RHA \| 40
CDCU877RHATG4	TI	获取价格	1.8-V PHASE LOCK LOOP CLOCK DRIVER

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