Datasheet > CDCU877ANMKT

CDCU877ANMKT

更新时间： 2024-11-19 02:49:27

品牌	Logo	应用领域
德州仪器 - TI		驱动
页数	文件大小	规格书
23页	1183K
描述
1.8-V PHASE LOCK LOOP CLOCK DRIVER

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CDCU877ANMKT 数据手册

CDCU877, CDCU877A

1.8-V PHASE LOCK LOOP CLOCK DRIVER

www.ti.com

SCAS688D–JUNE 2005–REVISED JULY 2007

FEATURES

•

Low Static Phase Offset: ±50 ps

•

1.8-V Phase Lock Loop Clock Driver for

Double Data Rate (DDR II) Applications

Distributes One Differential Clock Input to Ten

Differential Outputs

•

Spread Spectrum Clock Compatible

Operating Frequency: 10 MHz to 400 MHz

Low Current Consumption: <135 mA

Low Jitter (Cycle-Cycle): ±30 ps

Low Output Skew: 35 ps

•

52-Ball μBGA (MicroStar™ Junior BGA,

0,65-mm pitch) and 40-Pin MLF

External Feedback Pins (FBIN, FBIN) are Used

to Synchronize the Outputs to the Input

Clocks

•

Meets or Exceeds JESD82-8 PLL Standard for

PC2-3200/4300

Low Period Jitter: ±20 ps

Low Dynamic Phase Offset: ±15 ps

Fail-Safe Inputs

DESCRIPTION

The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock

input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock

outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks

(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AV_DD). When OE is low, the

clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in

frequency. OS (output select) is a program pin that must be tied to GND or V_DD. When OS is high, OE functions

as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.

When AV_DDis grounded, the PLL is turned off and bypassed for test purposes.

When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection

circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low

power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being

logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the

PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within

the specified stabilization time.

The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from

—40°C to 85°C.

ORDERING INFORMATION

(1)

T_A

52-BALL BGA

CDCU877ZQL

CDCU877AZQL

CDCU877GQL

CDCU877AGQL

40-Pin MLF

CDCU877RHA

CDCU877ARHA

CDCU877RTB

CDCU877ARTB

-40°C to 85°C

(1) For the most current package and ordering information, see the

Package Option Addendum at the end of this document, or see the

TI website at www.ti.com.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...23

中文翻译

下载PDF

与CDCU877ANMKT相关器件

型号	品牌	获取价格	描述	数据表
CDCU877ARHA	TI	获取价格	1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU877ARHAR	TI	获取价格	1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU877ARHARG4	TI	获取价格	1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU877ARHAT	TI	获取价格	1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 40-VQFN -40 to 85
CDCU877ARHATG4	TI	获取价格	1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 40-VQFN -40 to 85
CDCU877ARTB	TI	获取价格	1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU877ARTBR	TI	获取价格	1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 40-VQFN -40 to 85
CDCU877ARTBT	TI	获取价格	877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40, 6 X 6
CDCU877AZQL	TI	获取价格	1.8V PHASE LOCK LOOP CLOCK DRIVER
CDCU877AZQLR	TI	获取价格	暂无描述

与CDCU877ANMKT相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

18
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

12
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

43
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

38

产品中心

服务支持

精选活动

关于我们

帮助中心

CDCU877ANMKT

CDCU877ANMKT 数据手册

与CDCU877ANMKT相关器件

与CDCU877ANMKT相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CDCU877ANMKT

CDCU877ANMKT 数据手册

与CDCU877ANMKT相关器件

与CDCU877ANMKT相关文章

您还可以找

您在本页遇到什么问题？