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CDCU877ARHARG4 PDF预览

CDCU877ARHARG4

更新时间： 2024-11-19 02:49:23
品牌 Logo 应用领域
德州仪器 - TI 驱动逻辑集成电路
页数 文件大小 规格书
23页 1183K
描述
1.8-V PHASE LOCK LOOP CLOCK DRIVER

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中文翻译

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CDCU877ARHARG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFN
包装说明：HVQCCN, LCC40,.24SQ,20针数：40
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.16系列：877
输入调节：DIFFERENTIALJESD-30 代码：S-PQCC-N40
JESD-609代码：e4长度：6 mm
逻辑集成电路类型：PLL BASED CLOCK DRIVER最大I（ol）：0.009 A
湿度敏感等级：3功能数量：1
反相输出次数：端子数量：40
实输出次数：10最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：HVQCCN
封装等效代码：LCC40,.24SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE包装方法：TR
峰值回流温度（摄氏度）：260电源：1.8 V
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.035 ns
座面最大高度：1 mm子类别：Clock Drivers
最大供电电压 (Vsup)：1.9 V最小供电电压 (Vsup)：1.7 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6 mm最小 fmax：340 MHz
Base Number Matches：1

CDCU877ARHARG4 数据手册

 浏览型号CDCU877ARHARG4的Datasheet PDF文件第2页浏览型号CDCU877ARHARG4的Datasheet PDF文件第3页浏览型号CDCU877ARHARG4的Datasheet PDF文件第4页浏览型号CDCU877ARHARG4的Datasheet PDF文件第5页浏览型号CDCU877ARHARG4的Datasheet PDF文件第6页浏览型号CDCU877ARHARG4的Datasheet PDF文件第7页 
CDCU877, CDCU877A  
1.8-V PHASE LOCK LOOP CLOCK DRIVER  
www.ti.com  
SCAS688D–JUNE 2005–REVISED JULY 2007  
FEATURES  
•
•
Low Static Phase Offset: ±50 ps  
•
1.8-V Phase Lock Loop Clock Driver for  
Double Data Rate (DDR II) Applications  
Distributes One Differential Clock Input to Ten  
Differential Outputs  
•
•
•
•
•
•
•
Spread Spectrum Clock Compatible  
Operating Frequency: 10 MHz to 400 MHz  
Low Current Consumption: <135 mA  
Low Jitter (Cycle-Cycle): ±30 ps  
Low Output Skew: 35 ps  
•
•
52-Ball μBGA (MicroStar™ Junior BGA,  
0,65-mm pitch) and 40-Pin MLF  
External Feedback Pins (FBIN, FBIN) are Used  
to Synchronize the Outputs to the Input  
Clocks  
•
•
Meets or Exceeds JESD82-8 PLL Standard for  
PC2-3200/4300  
Low Period Jitter: ±20 ps  
Low Dynamic Phase Offset: ±15 ps  
Fail-Safe Inputs  
DESCRIPTION  
The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock  
input pair (CK, CK) to ten differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock  
outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks  
(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the  
clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in  
frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions  
as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.  
When AVDD is grounded, the PLL is turned off and bypassed for test purposes.  
When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection  
circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low  
power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being  
logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the  
PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within  
the specified stabilization time.  
The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from  
—40°C to 85°C.  
ORDERING INFORMATION  
(1)  
TA  
52-BALL BGA  
CDCU877ZQL  
CDCU877AZQL  
CDCU877GQL  
CDCU877AGQL  
40-Pin MLF  
CDCU877RHA  
CDCU877ARHA  
CDCU877RTB  
CDCU877ARTB  
-40°C to 85°C  
(1) For the most current package and ordering information, see the  
Package Option Addendum at the end of this document, or see the  
TI website at www.ti.com.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
MicroStar is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2005–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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中文翻译

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CDCU877ARHARG4 替代型号

型号 品牌 替代类型 描述 数据表
CDCU877ARHAR TI

完全替代

 1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU877ARHAT TI

完全替代

 1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 40-VQFN -40 to 85

与CDCU877ARHARG4相关器件

型号 品牌 获取价格 描述 数据表
CDCU877ARHAT TI

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 		1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 40-VQFN -40 to 85
CDCU877ARHATG4 TI

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 		1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 40-VQFN -40 to 85
CDCU877ARTB TI

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 		1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU877ARTBR TI

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 		1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 40-VQFN -40 to 85
CDCU877ARTBT TI

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 		877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC40, 6 X 6
CDCU877AZQL TI

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 		1.8V PHASE LOCK LOOP CLOCK DRIVER
CDCU877AZQLR TI

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 		暂无描述
CDCU877AZQLT TI

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 		暂无描述
CDCU877B SEME-LAB

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 		1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU877BZQLR TI

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 		1.8V Phase-Lock Loop Clock Driver for DDR2 SDRAM Applications 52-BGA MICROSTAR JUNIOR -40

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