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CDCS503TPWRQ1 PDF预览

CDCS503TPWRQ1

更新时间: 2024-09-16 12:42:59
品牌 Logo 应用领域
德州仪器 - TI 时钟
页数 文件大小 规格书
14页 527K
描述
Clock Buffer/Clock Multiplier With Optional SSC

CDCS503TPWRQ1 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:TSSOP,针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.74系列:CDC
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e4长度:3 mm
负载电容(CL):15 pF逻辑集成电路类型:PLL BASED CLOCK DRIVER
最大I(ol):0.012 A湿度敏感等级:3
功能数量:1反相输出次数:
端子数量:8实输出次数:1
最高工作温度:105 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
筛选级别:AEC-Q100座面最大高度:1.2 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mm最小 fmax:108 MHz
Base Number Matches:1

CDCS503TPWRQ1 数据手册

 浏览型号CDCS503TPWRQ1的Datasheet PDF文件第2页浏览型号CDCS503TPWRQ1的Datasheet PDF文件第3页浏览型号CDCS503TPWRQ1的Datasheet PDF文件第4页浏览型号CDCS503TPWRQ1的Datasheet PDF文件第5页浏览型号CDCS503TPWRQ1的Datasheet PDF文件第6页浏览型号CDCS503TPWRQ1的Datasheet PDF文件第7页 
CDCS503-Q1  
www.ti.com  
SCAS924B MARCH 2012REVISED JUNE 2012  
Clock Buffer/Clock Multiplier With Optional SSC  
Check for Samples: CDCS503-Q1  
1
FEATURES  
Qualified for Automotive Applications  
Output Disable Through Control Pin  
AEC-Q100 Test Guidance With the Following  
Results:  
Single 3.3 V Device Power Supply  
Wide Temperature Range –40°C to 105°C  
Device Temperature Grade 2  
Low Space Consumption 8-Pin TSSOP  
Package  
-40°C to 105°C Ambient Operating  
Temperature Range  
APPLICATIONS  
Device HBM ESD Classification Level H2  
Device CDM ESD Classification Level C3B  
Automotive Applications Requiring EMI  
Reduction Through SSC and/or Clock  
Multiplication  
Part of a Family of Easy to Use Clock  
Generator Devices With Optional Spread  
Spectrum Clocking (SSC)  
IN  
SSC_SEL 0  
SSC_SEL 1  
VDD  
OE  
1
2
3
4
8
7
6
5
Clock Multiplier With Selectable Output  
Frequency and Selectable SSC  
CDCS503-Q1  
OUT  
FS  
SSC Controllable Through Two External Pins  
GND  
±0%, ±0.5%, ±1%, ±2% Center Spread  
Frequency Multiplication Selectable Between  
x1 or x4 With One External Control Pin  
V
DD  
GND  
LV  
CMOS  
x1 or x4  
/ SSC  
LVCMOS  
IN  
OUT  
SSC_SEL 0  
SSC_SEL 1  
FS  
Control  
Logic  
OE  
Figure 1. BLOCK DIAGRAM  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2012, Texas Instruments Incorporated  
 

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