Datasheet > CDCS503PWR

CDCS503PWR

更新时间： 2024-09-17 11:06:27

品牌	Logo	应用领域
德州仪器 - TI		时钟倍频器
页数	文件大小	规格书
9页	300K
描述
具有可选 SSC 的时钟缓冲器/时钟倍频器 \| PW \| 8 \| -40 to 85

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替代型号

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CDCS503PWR 数据手册

CDCS503

www.ti.com .................................................................................................................................................................................................. SCAS872–MARCH 2009

Clock Buffer/Clock Multiplier With Optional SSC

FEATURES

APPLICATIONS

•

Consumer and Industrial Applications

requiring EMI reduction through Spread

Spectrum Clocking and/ or Clock

Multiplication

•

Part of a Family of Easy to use Clock

Generator Devices With Optional SSC

Clock Multiplier With Selectable Output

Frequency and Selectable SSC

SSC Controllable via 2 External Pins

PACKAGE

–

±0%, ±0.5%, ±1%, ±2% Center Spread

V_DD

•

Frequency Multiplication Selectable Between

x1 or x4 With One External Control Pin

SSC_SEL 0

SSC_SEL 1

CDCS503

OUT

•

Output Disable via Control Pin

GND

Single 3.3V Device Power Supply

Wide Temperature Range –40°C to 85°C

Low Space Consumption by 8 Pin TSSOP

Package

BLOCK DIAGRAM

GND

CMOS

x1 or x4

/ SSC

LVCMOS

OUT

SSC_SEL 0

SSC_SEL 1

Control

Logic

DESCRIPTION

The CDCS503 is a spread spectrum capable, LVCMOS Input Clock Buffer with selectable frequency

multiplication.

It shares major functionality with the CDCS502 but utilizes a LVCMOS input stage instead of the crystal input

stage of the CDCS502. Also an Output Enable pin has been added to the CDCS503.

The device accepts a 3.3V LVCMOS signal at the input.

The input signal is processed by a PLL, whose output frequency is either equal to the input frequency or

multiplied by the factor of 4.

The PLL is also able to spread the clock signal by ±0%, ±0.5%, ±1% or ±2% centered around the output clock

frequency with a triangular modulation.

By this, the device can generate output frequencies between 8MHz and 108MHz with or without SSC.

A separate control pin can be used to enable or disable the output. The CDCS503 operates in 3.3V environment.

It is characterized for operation from –40°C to 85°C, and available in an 8-pin TSSOP package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...9

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CDCS503PWR 替代型号

型号	品牌	替代类型	描述	数据表
CDCS503PW	TI	完全替代	具有可选 SSC 的时钟缓冲器/时钟倍频器 \| PW \| 8 \| -40 to 85

与CDCS503PWR相关器件

型号	品牌	获取价格	描述	数据表
CDCS503-Q1	TI	获取价格	Clock Buffer/Clock Multiplier With Optional SSC
CDCS503TPWRQ1	TI	获取价格	Clock Buffer/Clock Multiplier With Optional SSC
CDCS504-Q1	TI	获取价格	时钟缓冲器/时钟倍频器
CDCS504TPWRQ1	TI	获取价格	时钟缓冲器/时钟倍频器 \| PW \| 8 \| -40 to 105
CDCU2A877	TI	获取价格	1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU2A877_1	TI	获取价格	1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU2A877NMKR	TI	获取价格	适用于 DDR2 SDRAM 应用且具有高输出驱动的 1.8V 锁相环路时钟驱动器 \| N
CDCU2A877NMKT	TI	获取价格	适用于 DDR2 SDRAM 应用且具有高输出驱动的 1.8V 锁相环路时钟驱动器 \| N
CDCU2A877ZQL	TI	获取价格	1.8-V PHASE LOCK LOOP CLOCK DRIVER
CDCU2A877ZQLR	TI	获取价格	1.8-V PHASE LOCK LOOP CLOCK DRIVER

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