CDCP1803MRGETEP

更新时间： 2024-09-15 12:55:11

品牌	Logo	应用领域
德州仪器 - TI		时钟
页数	文件大小	规格书
24页	595K
描述
1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER

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CDCP1803MRGETEP 数据手册

CDCP1803-EP

www.ti.com ........................................................................................................................................................................................... SCAS864–DECEMBER 2008

1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER

FEATURES

RGE PACKAGE

•

Distributes One Differential Clock Input to

Three LVPECL Differential Clock Outputs

(TOP VIEW)

•

Programmable Output Divider for Two LVPECL

Outputs

•

Low-Output Skew 15 ps (Typical)

V_CCRange 3 V–3.6 V

24 23 22 21 20 19

V_DDPECL

V_DD

Signaling Rate Up to 800-MHz LVPECL

Differential Input Stage for Wide

Common-Mode Range

(

V_SS

•

Provides VBB Bias Voltage Output for

Single-Ended Input Signals

V_DDPECL

VBB

V_DD

V_SS

•

Receiver Input Threshold ±75 mV

10 11 12

24-Terminal QFN Package (4 mm × 4 mm)

Accepts Any Differential Signaling:

LVDS, HSTL, CML, VML, SSTL-2, and

Single-Ended: LVTTL/LVCMOS

⁽²⁾Thermal pad must be connected to V_SS

P0024-02

SUPPORTS DEFENSE, AEROSPACE,

AND MEDICAL APPLICATIONS

•

Controlled Baseline

One Assembly/Test Site

One Fabrication Site

Available in Military (–55°C/125°C)

Temperature Range⁽¹⁾

•

Extended Product Life Cycle

Extended Product-Change Notification

Product Traceability

(1) Additional temperature ranges available - contact factory

DESCRIPTION/ORDERING INFORMATION

The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential

clock outputs Y[2:0] and Y[2:0] with minimum skew for clock distribution. The CDCP1803 is specifically designed

for driving 50-Ω transmission lines.

The CDCP1803 has three control terminals, S0, S1, and S2, to select different output mode settings; see Table 1

for details. The CDCP1803 is characterized for operation from –55°C to 125°C. For use in single-ended driver

applications, the CDCP1803 also provides a VBB output terminal that can be directly connected to the unused

input as a common-mode voltage reference.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...24

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CDCP1803MRGETEP 替代型号

型号	品牌	替代类型	描述	数据表
V62/09619-01XE	TI	功能相似	1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER

与CDCP1803MRGETEP相关器件

型号	品牌	获取价格	描述	数据表
CDCP1803RGER	TI	获取价格	1:3 LVPECL Clock Buffer with Programable Divider 24-VQFN -40 to 85
CDCP1803RGERG4	TI	获取价格	1:3 LVPECL Clock Buffer with Programable Divider 24-VQFN -40 to 85
CDCP1803RGET	TI	获取价格	具有可编程分频器的 1:3 LVPECL 时钟缓冲器 \| RGE \| 24 \| -40 t
CDCP1803RGETG4	TI	获取价格	具有可编程分频器的 1:3 LVPECL 时钟缓冲器 \| RGE \| 24 \| -40 t
CDCP1803RTHR	TI	获取价格	1:3 LVPECL Clock Buffer with Programable Divider 24-VQFN -40 to 85
CDCR61A	TI	获取价格	DIRECT RAMBUSE CLOCK GENERATOR- LITE
CDCR61APW	TI	获取价格	DIRECT RAMBUSE CLOCK GENERATOR- LITE
CDCR61APWG4	TI	获取价格	Direct RAMBus Clock Generator - Lite 16-TSSOP -40 to 85
CDCR61APWR	TI	获取价格	Direct RAMBus 时钟发生器 - Lite 版 \| PW \| 16 \| -40
CDCR81	TI	获取价格	DIRECT RAMBUSE CLOCK GENERATOR

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