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CDCR81DBQ PDF预览

CDCR81DBQ

更新时间： 2024-09-14 22:40:11
品牌 Logo 应用领域
德州仪器 - TI 晶体时钟发生器微控制器和处理器外围集成电路光电二极管
页数 文件大小 规格书
13页 184K
描述
DIRECT RAMBUSE CLOCK GENERATOR

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中文翻译

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CDCR81DBQ 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：PLASTIC, SSOP-24针数：24
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.9
Is Samacsys：NJESD-30 代码：R-PDSO-G24
长度：8.65 mm端子数量：24
最高工作温度：70 °C最低工作温度：
最大输出时钟频率：400 MHz封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP24,.24
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
主时钟/晶体标称频率：100 MHz认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Clock Generators
最大压摆率：70 mA最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.9 mm
uPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches：1

CDCR81DBQ 数据手册

 浏览型号CDCR81DBQ的Datasheet PDF文件第2页浏览型号CDCR81DBQ的Datasheet PDF文件第3页浏览型号CDCR81DBQ的Datasheet PDF文件第4页浏览型号CDCR81DBQ的Datasheet PDF文件第5页浏览型号CDCR81DBQ的Datasheet PDF文件第6页浏览型号CDCR81DBQ的Datasheet PDF文件第7页 
CDCR81  
DIRECT RAMBUS CLOCK GENERATOR  
SCAS606B – NOVEMBER 1998 – REVISED NOVEMBER 1999  
DBQ PACKAGE  
(TOP VIEW)  
300-MHz Differential Clock Source for  
Direct RAMBUS Memory Systems for an  
600-MHz Data Transfer Rate  
V
IR  
S0  
S1  
V
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
DD  
Synchronizes the Clock Domains of the  
Rambus Channel With an External System  
or Processor Clock  
REFCLK  
2
V
P
O
3
DD  
DD  
GNDP  
GNDI  
GNDO  
CLK  
4
Three Power Operating Modes to Minimize  
Power for Mobile and Other  
Power-Sensitive Applications  
5
PCLKM  
SYNCLKN  
GNDC  
NC  
6
CLKB  
GNDO  
7
8
Operates From a Single 3.3-V Supply and  
120-mW at 300 MHz (Typ)  
V
C
V
O
9
DD  
DD  
V
IPD  
MULT0  
MULT1  
10  
11  
DD  
STOPB  
Packaged in a Shrink Small-Outline  
Package (DBQ)  
PWRDNB 12  
13 S2  
Wide Phase-Lock Input Frequency Range  
33 MHz to 100 MHz  
NC – No internal connection  
No External Components Required for PLL  
Supports Independent Channel Clocking  
Spread Spectrum Clocking Tracking  
Capability to Reduce EMI  
Designed For Use With TI’s 133-MHz Clock  
Synthesizers CDC925, CDC924, CDC922  
and CDC921  
description  
The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus  
memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system  
or processor clock. It is designed to support Direct Rambus memory on desktop, workstation, server and mobile  
PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus memory  
applications.  
The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to  
enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct  
Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the  
DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK  
to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK  
frequencies by ratios M and N such that PCLK/M = SYNCLK/N, where SYNCLK = BUSCLK/4. The DRCG  
detects the phase difference between PCLK/M and SYNCLK/N and adjusts the phase of BUSCLK such that  
the skew between PCLK/M and SYNCLK/N is minimized. This allows data to be transferred across the  
SYNCLK/PCLK boundary without incurring additional latency.  
User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of  
one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 400 MHz  
with clock references ranging from 33 MHz to 100 MHz. The CDCR81 meets Rambus Clock Generator,  
Revision 1.0 specification up to 300 MHz. The mode select terminals can be used to select a bypass mode  
where the frequency multiplied reference clock is directly output to the Rambus channel for systems where  
synchronization between the Rambus clock and a system clock is not required. Test modes are provided to  
bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a high-impedance state  
for board testing.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Direct Rambus and Rambus are trademarks of Rambus Inc.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

中文翻译

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