CDCR83
DIRECT RAMBUS CLOCK GENERATOR
SCAS632A – APRIL 2001 – REVISED MARCH 2002
D
D
D
400-MHz Differential Clock Source for
Direct Rambus Memory Systems for an
800-MHz Data Transfer Rate
D
D
D
Cycle-Cycle Jitter Is Less Than 50 ps at
400 MHz
Certified by Gigatest Labs to Exceed the
Rambus DRCG Validation Requirement
Synchronizes the Clock Domains of the
Rambus Channel With an External System
or Processor Clock
Supports Industrial Temperature Range of
°
°
–40 C to 85 C
Three Power Operating Modes to Minimize
Power for Mobile and Other
Power-Sensitive Applications
DBQ PACKAGE
(TOP VIEW)
V
IR
S0
S1
V
D
D
D
D
D
D
Operates From a Single 3.3-V Supply and
120 mW at 300 MHz (Typ)
1
24
23
22
21
20
19
18
17
16
15
14
DD
REFCLK
2
V
P
O
3
Packaged in a Shrink Small-Outline
Package (DBQ)
DD
DD
GNDP
GNDI
GNDO
CLK
4
5
Supports Frequency Multipliers: 4, 6, 8,
16/3
PCLKM
SYNCLKN
GNDC
NC
6
CLKB
GNDO
7
No External Components Required for PLL
Supports Independent Channel Clocking
8
V
C
V
O
9
DD
DD
Spread Spectrum Clocking Tracking
Capability to Reduce EMI
V
IPD
MULT0
MULT1
10
11
DD
STOPB
D
Designed for Use With TI’s 133-MHz Clock
Synthesizers CDC924 and CDC921
PWRDNB 12
13 S2
NC – No internal connection
description
The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus
memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system
or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and
mobile PC motherboards. DRCG also provides an off-the-shelf solution for a broad range of Direct Rambus
memory applications.
The DRCG provides clock multiplication and phase alignment for a Direct Rambus memory subsystem to
enable synchronous communication between the Rambus channel and ASIC clock domains. In a Direct
Rambus memory subsystem, a system clock source provides the REFCLK and PCLK clock references to the
DRCG and memory controller, respectively. The DRCG multiplies REFCLK and drives a high-speed BUSCLK
to RDRAMs and the memory controller. Gear ratio logic in the memory controller divides the PCLK and BUSCLK
frequenciesbyratiosMandNsuchthatPCLKM=SYNCLKN, whereSYNCLK=BUSCLK/4. TheDRCGdetects
the phase difference between PCLKM and SYNCLKN and adjusts the phase of BUSCLK such that the skew
between PCLKM and SYNCLKN is minimized. This allows data to be transferred across the SYNCLK/PCLK
boundary without incurring additional latency.
User control is provided by multiply and mode selection terminals. The multiply terminals provide selection of
one of four clock frequency multiply ratios, generating BUSCLK frequencies ranging from 267 MHz to 400 MHz
with clock references ranging from 33 MHz to 100 MHz. The mode select terminals can be used to select a
bypass mode where the frequency multiplied reference clock is directly output to the Rambus channel for
systems where synchronization between the Rambus clock and a system clock is not required. Test modes are
provided to bypass the PLL and output REFCLK on the Rambus channel and to place the outputs in a
high-impedance state for board testing.
The CDCR83 is characterized for operation over free-air temperatures of –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Direct Rambus and Rambus are trademarks of Rambus Inc.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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