CDCP1803RGET

更新时间： 2024-11-19 11:07:55

品牌	Logo	应用领域
德州仪器 - TI		时钟
页数	文件大小	规格书
19页	307K
描述
具有可编程分频器的 1:3 LVPECL 时钟缓冲器 \| RGE \| 24 \| -40 to 85

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中文翻译

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数据手册
替代型号

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CDCP1803RGET 数据手册

ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢆ

ꢃ ꢇꢆ ꢈꢉꢂ ꢊꢀꢈ ꢀꢈ ꢋ ꢀꢌ ꢍ ꢎꢏ ꢏꢊ ꢐ

ꢑ ꢒꢓ ꢔ ꢂꢐ ꢋꢕ ꢐꢖꢗ ꢗ ꢖꢍꢈ ꢊ ꢁ ꢒꢉ ꢒ ꢁꢊ ꢐ

SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004

MLF PACKAGE

(TOP VIEW)

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Distributes One Differential Clock Input to

Three LVPECL Differential Clock Outputs

Programmable Output Divider for Two

LVPECL Outputs

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Low-Output Skew 15 ps (Typical)

Range 3 V−3.6 V

VddPECL

17 Vdd1

Signaling Rate Up to 800-MHz LVPECL

Differential Input Stage for Wide

Common-Mode Range

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ꢀ

Provides VBB Bias Voltage Output for

Single-Ended Input Signals

15 Y1

14 Vdd1

VddPECL

VBB

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Receiver Input Threshold + 75 mV

24-Pin MLF Package (4 mm x 4 mm)

Accepts Any Differential Signaling: LVDS,

HSTL, CML, VML, SSTL-2, and

Single-Ended: LVTTL/LVCMOS

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description

PowerPad must be connected to V

The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential

clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCP1803 is specifically

designed for driving 50-Ω transmission lines.

The CDCP1803 has three control pins, S0, S1, and S2, to select different output mode settings, see Table 1

for details. The CDCP1803 is characterized for operation from −40°C to 85°C. For use in single-ended driver

applications, the CDCP1803 also provides a VBB output pin that can be directly connected to the unused input

as a common-mode voltage reference.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...19

中文翻译

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CDCP1803RGET 替代型号

型号	品牌	替代类型	描述	数据表
CDCP1803RGETG4	TI	完全替代	具有可编程分频器的 1:3 LVPECL 时钟缓冲器 \| RGE \| 24 \| -40 t
CDCP1803RGERG4	TI	完全替代	1:3 LVPECL Clock Buffer with Programable Divider 24-VQFN -40 to 85
CDCP1803RGER	TI	完全替代	1:3 LVPECL Clock Buffer with Programable Divider 24-VQFN -40 to 85

与CDCP1803RGET相关器件

型号	品牌	获取价格	描述	数据表
CDCP1803RGETG4	TI	获取价格	具有可编程分频器的 1:3 LVPECL 时钟缓冲器 \| RGE \| 24 \| -40 t
CDCP1803RTHR	TI	获取价格	1:3 LVPECL Clock Buffer with Programable Divider 24-VQFN -40 to 85
CDCR61A	TI	获取价格	DIRECT RAMBUSE CLOCK GENERATOR- LITE
CDCR61APW	TI	获取价格	DIRECT RAMBUSE CLOCK GENERATOR- LITE
CDCR61APWG4	TI	获取价格	Direct RAMBus Clock Generator - Lite 16-TSSOP -40 to 85
CDCR61APWR	TI	获取价格	Direct RAMBus 时钟发生器 - Lite 版 \| PW \| 16 \| -40
CDCR81	TI	获取价格	DIRECT RAMBUSE CLOCK GENERATOR
CDCR81_08	TI	获取价格	CDCR81_08
CDCR81DBQ	TI	获取价格	DIRECT RAMBUSE CLOCK GENERATOR
CDCR81DBQR	TI	获取价格	CDCR81_08

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