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CDCP1803RGER PDF预览

CDCP1803RGER

更新时间: 2024-11-18 13:06:47
品牌 Logo 应用领域
德州仪器 - TI 时钟
页数 文件大小 规格书
19页 307K
描述
1:3 LVPECL Clock Buffer with Programable Divider 24-VQFN -40 to 85

CDCP1803RGER 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFN
包装说明:QFN-24针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:5.34
Is Samacsys:N系列:1803
输入调节:DIFFERENTIALJESD-30 代码:S-PQCC-N24
JESD-609代码:e4长度:4 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:2
功能数量:1反相输出次数:
端子数量:24实输出次数:3
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC24,.16SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法:TR峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:0.6 ns
传播延迟(tpd):0.6 ns认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.03 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4 mm
最小 fmax:800 MHzBase Number Matches:1

CDCP1803RGER 数据手册

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SCAS727B − NOVEMBER 2003 − REVISED FEBRUARY 2004  
MLF PACKAGE  
(TOP VIEW)  
Distributes One Differential Clock Input to  
Three LVPECL Differential Clock Outputs  
Programmable Output Divider for Two  
LVPECL Outputs  
Low-Output Skew 15 ps (Typical)  
V
Range 3 V−3.6 V  
CC  
EN  
VddPECL  
IN  
S0  
17 Vdd1  
Y1  
1
2
3
4
5
6
18  
Signaling Rate Up to 800-MHz LVPECL  
Differential Input Stage for Wide  
Common-Mode Range  
16  
V
SS  
Provides VBB Bias Voltage Output for  
Single-Ended Input Signals  
15 Y1  
14 Vdd1  
13  
IN  
VddPECL  
VBB  
Receiver Input Threshold + 75 mV  
24-Pin MLF Package (4 mm x 4 mm)  
V
SS  
Accepts Any Differential Signaling: LVDS,  
HSTL, CML, VML, SSTL-2, and  
Single-Ended: LVTTL/LVCMOS  
description  
PowerPad must be connected to V  
.
SS  
The CDCP1803 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential  
clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCP1803 is specifically  
designed for driving 50-transmission lines.  
The CDCP1803 has three control pins, S0, S1, and S2, to select different output mode settings, see Table 1  
for details. The CDCP1803 is characterized for operation from −40°C to 85°C. For use in single-ended driver  
applications, the CDCP1803 also provides a VBB output pin that can be directly connected to the unused input  
as a common-mode voltage reference.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢓꢤ  
Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

CDCP1803RGER 替代型号

型号 品牌 替代类型 描述 数据表
CDCP1803RGET TI

完全替代

具有可编程分频器的 1:3 LVPECL 时钟缓冲器 | RGE | 24 | -40 t
CDCP1803RGETG4 TI

完全替代

具有可编程分频器的 1:3 LVPECL 时钟缓冲器 | RGE | 24 | -40 t
CDCP1803RGERG4 TI

完全替代

1:3 LVPECL Clock Buffer with Programable Divider 24-VQFN -40 to 85

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CDCP1803RGETG4 TI

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