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CDCM7005_13

更新时间： 2024-11-18 12:27:35
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德州仪器 - TI 时钟
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45页 1310K
描述
3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER

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CDCM7005_13 数据手册

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CDCM7005  
www.ti.com  
SCAS793E –JUNE 2005–REVISED FEBRUARY 2013  
3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER  
Check for Samples: CDCM7005  
1
FEATURES  
PIN ASSIGNMENTS (TOP VIEW)  
•
High Performance LVPECL and LVCMOS PLL  
Clock Synchronizer  
1
2
3
4
5
6
7
8
•
Two Reference Clock Inputs (Primary and  
Secondary Clock) for Redundancy Support  
With Manual or Automatic Selection  
CTRL_  
DATA  
A
B
C
D
E
F
PRI_REF REF_SEL VCC_CP CP_OUT CTRL_LE CTRL_CLK  
PLL_LOCK  
SEC_REF  
VBB  
GND  
GND  
GND  
GND  
GND  
VCC  
Y1A  
GND  
AVCC  
GND  
VCC  
GND  
VCC  
Y1B  
GND  
AVCC  
GND  
VCC  
GND  
VCC  
Y2A  
GND  
AVCC  
GND  
VCC  
GND  
VCC  
Y2B  
GND  
AVCC  
GND  
VCC  
GND  
VCC  
Y3A  
GND  
AVCC  
VCC  
VCC  
VCC  
VCC  
Y3B  
GND  
•
•
Accepts LVCMOS Input Frequencies Up to 200  
MHz  
STATUS_  
REF or  
PRI_SEC_  
CLK  
VCXO_IN Clock is Synchronized to One of the  
Two Reference Clocks  
STATUS_  
VCXO  
or  
VCXO_IN  
VCXO_IN  
Y0A  
•
•
VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)  
I_REF_CP  
Outputs Can Be a Combination of LVPECL and  
LVCMOS (Up to Five Differential LVPECL  
Outputs or Up to 10 LVCMOS Outputs)  
VCC  
Y4B  
Y4A  
•
•
Output Frequency is Selectable by x1, /2, /3, /4,  
/6, /8, /16 on Each Output Individually  
Y0B  
G
H
Efficient Jitter Cleaning From Low PLL Loop  
Bandwidth  
RESET  
or  
HOLD  
PD  
•
•
Low Phase Noise PLL Core  
P0022-01  
Programmable Phase Offset (PRI_REF and  
SEC_REF to Outputs)  
•
•
•
Wide Charge Pump Current Range From  
200 μA to 3 mA  
Dedicated Charge Pump Supply (VCC_CP) for  
Wide Tuning Voltage Range VCOs  
36 35 34 33 32 31 30 29 28 27 26 25  
37  
GND  
SEC_REF  
AVCC  
AVCC  
VBB  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
STATUS_REF or  
PRI_SEC_CLK  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
Presets Charge Pump to VCC_CP/2 for Fast  
Center-Frequency Setting of VC(X)O  
STATUS_VCXO or  
I_REF_CP  
VCC  
VCC  
VCC  
VCC  
Y4B  
Y4A  
VCC  
•
•
Analog and Digital PLL Lock Indication  
VCC  
Thermal Pad  
must be  
soldered to GND  
VCXO_IN  
VCXO_IN  
VCC  
Provides VBB Bias Voltage Output for Single-  
Ended Input Signals (VCXO_IN)  
•
•
Frequency Hold-Over Mode Improves Fail-Safe  
Operation  
VCC  
Y0A  
RESET or  
HOLD  
Y0B  
Power-Up Control Forces LVPECL Outputs to  
3-State at VCC < 1.5 V  
VCC  
VCC  
1
2
3
4
5
6
7
8
9
10 11 12  
•
•
•
SPI Controllable Device Setting  
3.3-V Power Supply  
P0023-01  
Packaged in 64-Pin BGA (0,8 mm Pitch – ZVA)  
or 48-Pin QFN (RGZ)  
•
Industrial Temperature Range –40°C to 85°C  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005–2013, Texas Instruments Incorporated  
 
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