是否无铅: | 不含铅 | 是否Rohs认证: | 符合 |
生命周期: | Active | 零件包装代码: | BGA |
包装说明: | LFBGA, | 针数: | 64 |
Reach Compliance Code: | compliant | ECCN代码: | EAR99 |
HTS代码: | 8542.39.00.01 | 风险等级: | 1.1 |
其他特性: | USER DEFINABLE FIVE DIFFERENTIAL LVPECL OUTPUT; DIFFERENTIAL VCO IN CLOCK | 系列: | 7005 |
输入调节: | SCHMITT TRIGGER MUX | JESD-30 代码: | S-PBGA-B64 |
JESD-609代码: | e1 | 长度: | 8 mm |
负载电容(CL): | 10 pF | 逻辑集成电路类型: | PLL BASED CLOCK DRIVER |
最大I(ol): | 0.008 A | 湿度敏感等级: | 3 |
功能数量: | 1 | 反相输出次数: | |
端子数量: | 64 | 实输出次数: | 5 |
最高工作温度: | 85 °C | 最低工作温度: | -40 °C |
输出特性: | 3-STATE | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | LFBGA | 封装形状: | SQUARE |
封装形式: | GRID ARRAY, LOW PROFILE, FINE PITCH | 包装方法: | TR |
峰值回流温度(摄氏度): | 260 | 最大电源电流(ICC): | 260 mA |
传播延迟(tpd): | 3 ns | 认证状态: | Not Qualified |
Same Edge Skew-Max(tskwd): | 2.4 ns | 座面最大高度: | 1.4 mm |
最大供电电压 (Vsup): | 3.6 V | 最小供电电压 (Vsup): | 3 V |
标称供电电压 (Vsup): | 3.3 V | 表面贴装: | YES |
温度等级: | INDUSTRIAL | 端子面层: | Tin/Silver/Copper (Sn/Ag/Cu) |
端子形式: | BALL | 端子节距: | 0.8 mm |
端子位置: | BOTTOM | 处于峰值回流温度下的最长时间: | NOT SPECIFIED |
宽度: | 8 mm | 最小 fmax: | 1500 MHz |
Base Number Matches: | 1 |
型号 | 品牌 | 替代类型 | 描述 | 数据表 |
CDCM7005ZVAR | TI |
完全替代 |
3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER | |
CDCM7005ZVA | TI |
类似代替 |
3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
CDCM9102 | TI |
获取价格 |
Low-Noise Two-Channel 100-MHz Clock Generator | |
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Low-Noise Two-Channel 100-MHz Clock Generator | |
CDCM9102RHBR | TI |
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Low-Noise Two-Channel 100-MHz Clock Generator | |
CDCM9102RHBT | TI |
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Low-Noise Two-Channel 100-MHz Clock Generator | |
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1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER | |
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1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER | |
CDCP1803MRGETEP | TI |
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1:3 LVPECL CLOCK BUFFER WITH PROGRAMMABLE DIVIDER | |
CDCP1803RGER | TI |
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1:3 LVPECL Clock Buffer with Programable Divider 24-VQFN -40 to 85 | |
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1:3 LVPECL Clock Buffer with Programable Divider 24-VQFN -40 to 85 | |
CDCP1803RGET | TI |
获取价格 |
具有可编程分频器的 1:3 LVPECL 时钟缓冲器 | RGE | 24 | -40 t |