CDCM7005-SP
www.ti.com
SGLS390E –JULY 2009–REVISED AUGUST 2012
3.3-V HIGH PERFORMANCE RAD-TOLERANT CLASS V,
CLOCK SYNCHRONIZER AND JITTER CLEANER
Check for Samples: CDCM7005-SP
1
FEATURES
•
High Performance LVPECL and LVCMOS PLL
Clock Synchronizer
•
•
QML-V Qualified, SMD 5962-07230
Military Temperature Range
(–55°C to 125°C Tcase
•
Two Reference Clock Inputs (Primary and
Secondary Clock) for Redundancy Support
With Manual or Automatic Selection
)
PIN ASSIGNMENTS
•
•
Accepts LVCMOS Input Frequencies Up to
200 MHz
HFG PACKAGE
(TOP VIEW)
VCXO_IN Clock is Synchronized to One of the
Two Reference Clocks
•
•
VCXO_IN Frequencies Up to 2 GHz (LVPECL)
Outputs Can Be a Combination of LVPECL and
LVCMOS (Up to Five Differential LVPECL
Outputs or Up to 10 LVCMOS Outputs)
•
•
Output Frequency is Selectable by x1, /2, /3, /4,
/6, /8, /16 on Each Output Individually
52 51 50 49 48 47 46 45 44 43 42 41 40
Efficient Jitter Cleaning From Low PLL Loop
Bandwidth
39
38
37
36
35
34
33
VCC
Y3B
Y3A
VCC
VCC
Y2B
Y2A
VCC
VCC
Y1B
Y1A
VCC
PD
GND
1
CTRL_DATA
AVCC
2
3
•
•
Low Phase Noise PLL Core
CTRL_CLK
CTRL_LE
AVCC
4
Programmable Phase Offset (PRI_REF and
SEC_REF to Outputs)
5
6
•
•
•
Wide Charge Pump Current Range From
200 μA to 3 mA
7
GND
32
31
30
29
28
27
8
CP_OUT
AVCC
9
Dedicated Charge Pump Supply (VCC_CP) for
Wide Tuning Voltage Range VCOs
10
11
12
13
VCC_CP
GND
Presets Charge Pump to VCC_CP/2 for Fast
Center Frequency Setting of VC(X)O
REF_SEL
GND
14 15 16 17 18 19 20 21 22 23 24 25 26
•
•
Analog and Digital PLL Lock Indication
Provides VBB Bias Voltage Output for Single-
Ended Input Signals (VCXO_IN)
•
•
Frequency Hold Over Mode Improves Fail-Safe
Operation
Power-Up Control Forces LVPECL Outputs to
3-State at VCC < 1.5 V
•
•
•
SPI Controllable Device Setting
3.3-V Power Supply
High-Performance 52 Pin Ceramic Quad Flat
Pack (HFG)
•
Rad-Tolerant : 50kRad (Si) TID
1
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