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CDCM7005

更新时间： 2024-11-17 22:29:23
品牌 Logo 应用领域
德州仪器 - TI 时钟
页数 文件大小 规格书
40页 1489K
描述
3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER

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CDCM7005 数据手册

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CDCM7005  
www.ti.com  
SCAS793A–JUNE 2005–REVISED JUNE 2005  
3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER  
FEATURES  
or 48-Pin QFN (RGZ)  
•
High Performance LVPECL and LVCMOS PLL  
Clock Synchronizer  
•
Industrial Temperature Range –40°C to 85°C  
PIN ASSIGNMENTS (TOP VIEW)  
•
Two Reference Clock Inputs (Primary and  
Secondary Clock) for Redundancy Support  
With Manual or Automatic Selection  
1
2
3
4
5
6
7
8
CTRL_  
A
B
C
D
E
F
PRI_REF REF_SEL VCC_CP CP_OUT CTRL_LE CTRL_CLK  
PLL_LOCK  
DATA  
•
•
•
•
Accepts LVCMOS Input Frequencies Up to  
200 MHz  
SEC_REF  
GND  
GND  
GND  
GND  
GND  
VCC  
Y1A  
GND  
AVCC  
GND  
VCC  
GND  
VCC  
Y1B  
GND  
AVCC  
GND  
VCC  
GND  
VCC  
Y2A  
GND  
AVCC  
GND  
VCC  
GND  
VCC  
Y2B  
GND  
AVCC  
GND  
VCC  
GND  
VCC  
Y3A  
GND  
AVCC  
VCC  
VCC  
VCC  
VCC  
Y3B  
GND  
VCXO_IN Clock is Synchronized to One of the  
Two Reference Clocks  
STATUS_  
REF or  
PRI_SEC_  
CLK  
VBB  
VCXO_IN Frequencies Up to 2.2 GHz  
(LVPECL)  
STATUS_  
VCXO  
or  
VCXO_IN  
VCXO_IN  
Y0A  
I_REF_CP  
Outputs Can Be a Combination of LVPECL  
and LVCMOS (Up to Five Differential LVPECL  
Outputs or Up to 10 LVCMOS Outputs)  
VCC  
Y4B  
Y4A  
•
•
Output Frequency is Selectable by x1, /2, /3,  
/4, /6, /8, /16 on Each Output Individually  
Efficient Jitter Cleaning From Low PLL Loop  
Bandwidth  
Y0B  
G
RESET  
or  
•
•
Low Phase Noise PLL Core  
PD  
H
HOLD  
Programmable Phase Offset (PRI_REF and  
SEC_REF to Outputs)  
P0022-01  
•
•
•
Wide Charge Pump Current Range From 200  
µA to 3 mA  
Dedicated Charge Pump Supply (VCC_CP) for  
Wide Tuning Voltage Range VCOs  
36 35 34 33 32 31 30 29 28 27 26 25  
37  
GND  
SEC_REF  
AVCC  
AVCC  
VBB  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Presets Charge Pump to VCC_CP/2 for Fast  
Center-Frequency Setting of VC(X)O  
STATUS_REF or  
PRI_SEC_CLK  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
STATUS_VCXO or  
I_REF_CP  
VCC  
VCC  
VCC  
VCC  
Y4B  
Y4A  
VCC  
•
•
Analog and Digital PLL Lock Indication  
VCC  
Provides VBB Bias Voltage Output for  
Single-Ended Input Signals (VCXO_IN)  
Thermal Pad  
must be  
VCXO_IN  
VCXO_IN  
VCC  
soldered to GND  
•
•
Frequency Hold-Over Mode Improves  
Fail-Safe Operation  
VCC  
Y0A  
RESET or  
HOLD  
Power-Up Control Forces LVPECL Outputs to  
3-State at VCC < 1.5 V  
Y0B  
VCC  
VCC  
1
2
3
4
5
6
7
8
9
10 11 12  
•
•
•
SPI Controllable Device Setting  
3.3-V Power Supply  
P0023-01  
Packaged in 64-Pin BGA (0,8 mm Pitch – ZVA)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2005, Texas Instruments Incorporated  
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CDCM7005 替代型号

型号 品牌 替代类型 描述 数据表
CDCE72010 TI

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