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ADP5040ACPZ-1-R7

更新时间： 2024-11-23 07:18:43
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亚德诺 - ADI 稳压器
页数 文件大小 规格书
40页 3565K
描述
Micro PMU with 1.2 A Buck Regulator

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ADP5040ACPZ-1-R7 数据手册

 浏览型号ADP5040ACPZ-1-R7的Datasheet PDF文件第2页浏览型号ADP5040ACPZ-1-R7的Datasheet PDF文件第3页浏览型号ADP5040ACPZ-1-R7的Datasheet PDF文件第4页浏览型号ADP5040ACPZ-1-R7的Datasheet PDF文件第5页浏览型号ADP5040ACPZ-1-R7的Datasheet PDF文件第6页浏览型号ADP5040ACPZ-1-R7的Datasheet PDF文件第7页 
Micro PMU with 1.2 A Buck Regulator  
and Two 300 mA LDOs  
Data Sheet  
ADP5040  
FEATURES  
GENERAL DESCRIPTION  
Input voltage range: 2.3 V to 5.5 V  
One 1.2 A buck regulator  
Two 300 mA LDOs  
20-lead, 4 mm × 4 mm LFCSP package  
Overcurrent and thermal protection  
Soft start  
The ADP5040 combines one high performance buck regulator  
and two low dropout regulators (LDO) in a small 20-lead  
LFCSP to meet demanding performance and board space  
requirements.  
The high switching frequency of the buck regulator enables the use  
of tiny multilayer external components and minimizes board space.  
Undervoltage lockout  
When the MODE pin is set to logic high, the buck regulator  
operates in forced pulse width modulation (PWM) mode.  
When the MODE pin is set to logic low, the buck regulator  
operates in PWM mode when the load is around the nominal  
value. When the load current falls below a predefined threshold  
the regulator operates in power save mode (PSM) improving  
the light-load efficiency. The low quiescent current, low  
dropout voltage, and wide input voltage range of the ADP5040  
LDOs extend the battery life of portable devices. The ADP5040  
LDOs maintain a power supply rejection greater than 60 dB for  
frequencies as high as 10 kHz while operating with a low headroom  
voltage.  
Buck key specifications  
Output voltage range: 0.8 V to 3.8 V  
Current mode topology for excellent transient response  
3 MHz operating frequency  
Peak efficiency up to 96%  
Uses tiny multilayer inductors and capacitors  
Mode pin selects forced PWM or auto PWM/PSM modes  
100% duty cycle low dropout mode  
LDOs key specifications  
Output voltage range: 0.8 V to 5.2 V  
Low VIN from 1.7 V to 5.5 V  
Stable with 2.2 µF ceramic output capacitors  
High PSRR  
Low output noise  
Each regulator in the ADP5040 is activated by a high level on  
the respective enable pin. The output voltages of the regulators  
are programmed though external resistor dividers to address a  
variety of applications.  
Low dropout voltage  
−40°C to +125°C junction temperature range  
FUNCTIONAL BLOCK DIAGRAM  
VOUT1  
R
= 30Ω  
L1  
1µH  
FILT  
AVIN  
SW  
V
AT  
OUT1  
1.2A  
FB1  
BUCK  
AVIN  
C6  
10µF  
R1  
R2  
VIN1  
V
= 2.3V TO  
5.5V  
IN1  
PGND  
MODE  
C5  
4.7µF  
EN_BK  
ON  
FPWM  
R3  
EN1  
OFF  
PSM/PWM  
VOUT2  
FB2  
V
AT  
LDO1  
(DIGITAL)  
OUT2  
VIN2  
V
= 1.7V  
TO 5.5V  
IN2  
300mA  
C1  
1µF  
C2  
2.2µF  
EN_LDO1  
R4  
ON  
ON  
EN2  
EN3  
OFF  
OFF  
EN_LDO2  
VOUT3  
FB3  
VIN3  
V
AT  
V
= 1.7V  
TO 5.5V  
OUT3  
IN3  
LDO2  
(ANALOG)  
300mA  
C3  
1µF  
C4  
2.2µF  
R7  
R3  
AGND  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2011 Analog Devices, Inc. All rights reserved.  
 
 
 
 
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ADP5040ACPZ-1-R7 替代型号

型号 品牌 替代类型 描述 数据表
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