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ADP5043

更新时间: 2024-11-24 02:52:07
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亚德诺 - ADI /
页数 文件大小 规格书
30页 1816K
描述
Micro PMU with 800 mA Buck, 300 mA LDO, Supervisory, Watchdog, and Manual Reset

ADP5043 数据手册

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Micro PMU with 800 mA Buck, 300 mA LDO,  
Supervisory, Watchdog, and Manual Reset  
Data Sheet  
ADP5043  
FEATURES  
GENERAL DESCRIPTION  
Input voltage range: 2.3 V to 5.5 V  
One 800 mA buck regulator  
One 300 mA LDO  
The ADP5043 combines one high performance buck regulator  
and one low dropout (LDO) regulator in a small 20-lead LFCSP  
to meet demanding performance and board space requirements.  
20-lead, 4 mm × 4 mm LFCSP package  
Initial regulator accuracy: 1ꢀ  
Overcurrent and thermal protection  
Soft start  
The high switching frequency of the buck regulator enables use of  
tiny multilayer external components and minimizes board space.  
The MODE pin selects the bucks mode of operation. When set  
to logic high, the buck regulator operates in forced PWM mode.  
When the MODE pin is set to logic low, the buck regulator  
operates in PWM mode when the load is around the nominal  
value. When the load current falls below a predefined threshold,  
the regulator operates in power save mode (PSM) improving the  
light-load efficiency.  
Undervoltage lockout  
Open-drain processor reset with threshold monitoring  
1.5ꢀ threshold accuracy over the full temperate range  
Guaranteed reset output valid to VCC = 1 V  
Dual watchdog for secure systems  
Watchdog 1 controls reset  
Watchdog 2 controls reset and regulators power cycle  
Buck regulator key specifications  
Current-mode topology for excellent transient response  
3 MHz operating frequency  
Uses tiny multilayer inductors and capacitors  
Mode pin selects forced PWM or auto PFM/PSM modes  
100ꢀ duty cycle low dropout mode  
LDO key specifications  
The low quiescent current, low dropout voltage, and wide input  
voltage range of the ADP5043 LDO extend the battery life of  
portable devices. The LDO maintains a power supply rejection  
of greater than 60 dB for frequencies as high as 10 kHz while  
operating with a low headroom voltage.  
Each regulator is activated by a high level on the respective  
enable pin. The ADP5043 is available with factory programmable  
default output voltages and can be set to a wide range of options.  
Low VIN from 1.7 V to 5.5 V  
The ADP5043 contains supervisory circuits that monitor  
power supply voltage levels and code execution integrity in  
microprocessor-based systems. The ADP5043 also provides  
power-on reset signals. An on-chip dual watchdog timer can  
reset the microprocessor or power cycle the system (Watchdog 2)  
if it fails to strobe within a preset timeout period.  
Stable with1 μF ceramic output capacitors  
High PSRR, 60 dB up to 1 kHz/10 kHz  
Low output noise  
Low dropout voltage: 150 mV at 300 mA load  
−40°C to +125°C junction temperature range  
HIGH LEVEL BLOCK DIAGRAM  
ADP5043  
AVIN  
L1  
1µH  
R
FILT  
30Ω  
AVIN  
VIN1  
SW  
V
@
OUT1  
800mA  
VOUT1  
PGND  
VIN1 = 2.3V  
TO 5.5V  
C6  
10µF  
BUCK  
EN_BK  
C5  
4.7µF  
ON  
ON  
FPWM  
MODE  
EN1  
OFF  
PSM/PWM  
VOUT2  
V
@
OUT2  
300mA  
VIN2  
VIN2 = 1.7V  
TO 5.5V  
LDO  
C2  
1µF  
C1  
1µF  
EN_LDO  
EN2  
OFF  
AVIN  
WSTAT  
nRSTO  
MR  
NC  
WDI1  
WDI2  
NC  
VIN  
WMOD  
WD1 MODE  
SELECTION  
GND  
AGND  
GND  
Figure 1.  
Rev. C  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2011–2019 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 

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