Datasheet > ADP5054-EVALZ

ADP5054-EVALZ

更新时间： 2024-02-25 06:20:07

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
31页	712K
描述
Quad Buck Regulator Integrated Power Solution

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ADP5054-EVALZ 数据手册

Quad Buck Regulator

Integrated Power Solution

Data Sheet

ADP5054

FEATURES

TYPICAL APPLICATION CIRCUIT

ADP5054

VREG

Wide input voltage range: 4.5 V to 15.5 V

1.5% output accuracy over full temperature range

250 kHz to 2 MHz adjustable switching frequency with

individual ½× frequency option

Power regulation

Channel 1 and Channel 2

Programmable 2 A/4 A/6 A sync buck regulators with

low-side FET drivers

Channel 3 and Channel 4: 2.5 A sync buck regulators

Flexible parallel operation

Single 12 A output (Channel 1 and Channel 2 in parallel)

Single 5 A output (Channel 3 and Channel 4 in parallel)

Low 1/f noise density

40 µV rms at 0.8 V_REFfor 10 Hz to 100 kHz

Precision enable with 0.811 V accurate threshold

Active output discharge switch

SYNC/MODE

INTERNAL

VDD

VREG

100mA

OSCILLATOR

FB1

PVIN1

BST1

SW1

4.5V TO 15.5V

CHANNEL 1

VOUT1

BUCK

COMP1

EN1

(2A/4A/6A)

VREG

DL1

VREG

CFG12

PGND

(SS, 1/2 × f_SW

PARALLEL)

DL2

SW2

CHANNEL 2

BUCK

(2A/4A/6A)

VOUT2

VREG

PVIN2

COMP2

BST2

FB2

EN2

PWRGD

PVIN3

BST3

SW3

VOUT3

C10

COMP3

EN3

CHANNEL 3

BUCK

(2A)

FB3

PGND3

VREG

CFG34

FPWM/PSM mode selection

BST4

SW4

(SS, 1/2 × f_SW

PARALLEL,

SCLKSET)

Frequency synchronization input or output

Power-good flag for Channel 1 output

UVLO, OCP, and TSD protection

C12

VOUT4

C13

CHANNEL 4

BUCK

(2A)

PVIN4

FB4

COMP4

C11

PGND4

EN4

48-lead, 7 mm × 7 mm LFCSP

EXPOSED PAD

−40°C to +125°C operational junctional temperature range

APPLICATIONS

Figure 1.

FPGA and processor applications

Small cell base stations

Security and surveillance

Medical applications

GENERAL DESCRIPTION

The ADP5054 combines four high performance buck regulators in

a 48-lead LFCSP package that meets demanding performance and

board space requirements. The device enables direct connection

to high input voltages of up to 15.5 V with no preregulators.

The switching frequency of the ADP5054 can be programmed

or synchronized to an external clock from 250 kHz to 2 MHz,

and an individual ½× frequency configuration is available for

each channel.

Channel 1 and Channel 2 integrate high-side power MOSFETs and

low-side MOSFET drivers. External NFETs can be used in low-side

power devices to achieve an efficiency optimized solution and

to deliver a programmable output current of 2 A, 4 A, or 6 A.

Combining Channel 1 and Channel 2 in a parallel configuration

provides a single output with up to 12 A of current.

The ADP5054 contains an individual precision enable pin on each

channel for easy power-up sequencing. The internal low 1/f noise

reference is implemented in the ADP5054 for noise sensitive

applications.

Table 1. Related Products

Model

Channels

I²C Package

Channel 3 and Channel 4 integrate both high-side and low-side

MOSFETs to deliver an output current of 2.5 A. Combining

Channel 3 and Channel 4 in a parallel configuration can

provide a single output with up to 5 A of current.

ADP5050

ADP5051

ADP5052

ADP5053

ADP5054

Four bucks, one LDO

Four bucks, supervisory Yes 48-Lead LFCSP

Four bucks, one LDO

Four bucks, supervisory No

Four high current bucks No

Yes 48-Lead LFCSP

48-Lead LFCSP

Rev. B

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

12 3 4 5 6 7...31

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