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ADP5051ACPZ-R7

更新时间： 2024-01-06 22:40:33
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
60页 1214K
描述
Integrated Power Solution with Quad Buck Regulators, Supervisory, and I<sup>2</sup>C Interface

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ADP5051ACPZ-R7 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN, LCC48,.28SQ,20
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：2.24其他特性：THRESHOLD VOLTAGE IS 0.5V
可调阈值：YES模拟集成电路 - 其他类型：POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码：S-XQCC-N48JESD-609代码：e3
长度：7 mm湿度敏感等级：3
信道数量：5功能数量：1
端子数量：48最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：UNSPECIFIED
封装代码：HVQCCN封装等效代码：LCC48,.28SQ,20
封装形状：SQUARE封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：260电源：12 V
认证状态：Not Qualified座面最大高度：0.8 mm
子类别：Power Management Circuits最大供电电流 (Isup)：6.35 mA
最大供电电压 (Vsup)：15 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：12 V表面贴装：YES
技术：DMOS温度等级：AUTOMOTIVE
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：7 mm
Base Number Matches：1

ADP5051ACPZ-R7 数据手册

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Integrated Power Solution with Quad Buck  
Regulators, Supervisory Circuit, and I2C Interface  
Data Sheet  
ADP5051  
FEATURES  
TYPICAL APPLICATION CIRCUIT  
ADP5051  
SYNC/MODE  
VREG  
Wide input voltage range: 4.5 V to 15.0 V  
1.5% output accuracy over full temperature range  
250 kHz to 1.4 MHz adjustable switching frequency  
Adjustable/fixed output options via factory fuse or I2C interface  
I2C interface with interrupt on fault conditions  
Power regulation  
Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A  
sync buck regulators with low-side FET driver  
Channel 3 and Channel 4: 1.2 A sync buck regulators  
Single 8 A output (Channel 1 and Channel 2 in parallel)  
Dynamic voltage scaling (DVS) for Channel 1 and Channel 4  
Precision enable with 0.8 V accurate threshold  
Active output discharge switch  
Programmable phase shift in 90° steps  
Individual channel FPWM/PSM selection  
Frequency synchronization input or output  
Optional latch-off protection on OVP/OCP failure  
Power-good flag on selected channels  
Low input voltage detection  
INT VREG  
100mA  
VDD  
OSCILLATOR  
RT  
C1  
C0  
FB1  
PVIN1  
4.5V TO 15V  
BST1  
SW1  
C3  
CHANNEL 1  
BUCK  
(4A)  
L1  
VOUT1  
C4  
C2  
COMP1  
VREG  
Q1  
Q2  
EN1  
DL1  
SS12  
R
ILIM1  
PGND  
DL2  
R
ILIM2  
PVIN2  
C5  
VREG  
CHANNEL 2  
BUCK  
(4A)  
VOUT2  
C7  
SW2  
COMP2  
L2  
C6  
C9  
BST2  
FB2  
EN2  
PVIN3  
BST3  
L3  
C8  
VOUT3  
C10  
SW3  
COMP3  
EN3  
CHANNEL 3  
BUCK  
(1.2A)  
FB3  
PGND3  
SS34  
BST4  
PVIN4  
C12  
L4  
VOUT4  
C13  
SW4  
FB4  
CHANNEL 4  
BUCK  
C11  
COMP4  
EN4  
(1.2A)  
VREG  
PGND4  
RSTO  
VTH  
Open-drain processor reset with external adjustable threshold  
monitoring  
WDI  
MR  
WATCHDOG  
AND  
RESET  
VOUTx  
Watchdog refresh input  
Manual reset input  
VDDIO  
PWRGD  
INT  
2
ALERT  
I
C
SCL  
SDA  
Overheat detection on junction temperature  
UVLO, OCP, and TSD protection  
EXPOSED PAD  
Figure 1.  
APPLICATIONS  
Combining Channel 1 and Channel 2 in a parallel configuration  
provides a single output with up to 8 A of current. Channel 3 and  
Channel 4 integrate both high-side and low-side MOSFETs to  
deliver an output current of 1.2 A.  
Small cell base stations  
FPGA and processor applications  
Security and surveillance  
Medical applications  
The ADP5051 supervisory circuits monitor the voltage level.  
The watchdog timer generates a reset when the WDI pin does  
not toggle within a preset timeout period. Select manual reset  
functionality via the processor reset mode or system power on/off  
switch mode.  
The optional I2C interface offers flexible configurations, including  
adjustable and fixed output voltage, junction temperature overheat  
warning, low input voltage detection, and dynamic voltage scaling.  
GENERAL DESCRIPTION  
The ADP5051 combines four high performance buck regulators  
and a supervisory circuit with a voltage monitor, a watchdog  
function, and a manual reset in a 48-lead LFCSP package that  
meets demanding performance and board space requirements.  
The device enables direct connection to high input voltages up to  
15.0 V with no preregulators.  
Table 1. Family Models  
Channel 1 and Channel 2 integrate high-side power MOSFET and  
low-side MOSFET drivers. In low-side power devices, use external  
NFETs to achieve an efficiency optimized solution and deliver a  
programmable output current of 1.2 A, 2.5 A, or 4 A.  
Model  
Channels  
I2C Package  
ADP5050  
ADP5051  
ADP5052  
ADP5053  
Four bucks, one LDO  
Four bucks, supervisory Yes 48-Lead LFCSP  
Four bucks, one LDO  
Four bucks, supervisory No  
Yes 48-Lead LFCSP  
No  
48-Lead LFCSP  
48-Lead LFCSP  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2013 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
 
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