Triple Buck Regulator
Integrated Power Solution
Data Sheet
ADP5056
FEATURES
TYPICAL APPLICATION CIRCUIT
Wide input voltage range: 2.75 V to 18 V
Bias input voltage range: 4.5 V to 18 V
RT
VBIAS
(V
= 4.5V
TO 18.0V)
BIAS
INT
REG
OSC
VREG
C1
V
SYNC/MODE
Operation up to 150°C junction temperature
−0.62% to +0.69% feedback voltage accuracy (−40°C to +125°C
junction temperature)
Channel 1 and Channel 2: 7 A synchronous buck regulator
(9.4 A minimum valley current limit)
Channel 1 and Channel 2: 14 A output in parallel operation
Channel 3: 3 A synchronous buck regulator (4.2 A minimum
valley current limit)
RAMP1
2.75V
TO 18.0V
BST1
C3
SW1
PVIN1
C2
L1
VOUT1
C4
CHANNEL 1
7A BUCK
FB1
COMP1
PGND
EN1
RAMP2
250 kHz to 2500 kHz adjustable switching frequency
External compensation for fast load transient response
Precision enable pin with 0.615 V accurate reference voltage
Programmable power-up and power-down sequence
Selective FPWM/PSM mode selection
BST2
PVIN2
C5
C6
L2
VOUT2
C7
SW2
FB2
CHANNEL 2
7A BUCK
COMP2
PGND
EN2
RAMP3
Frequency synchronization input or output
Power-good flag for three channels
Active output discharge switch
BST3
PVIN3
C8
C9
L3
VOUT3
C10
SW3
FB3
CHANNEL 3
3A BUCK
UVLO, overcurrent protection, and TSD protection
43-terminal, 5 mm × 5.5 mm LGA package
COMP3
PGND
EN3
APPLICATIONS
GND
GND
PWRGD
CFG1
LOGIC
Small cell base stations
Field programmable gate array (FPGA) and processor
applications
CFG2
GND
Security and surveillance
Medical applications
Figure 1.
GENERAL DESCRIPTION
The ADP5056 combines three high performance buck regulators
in a 43-terminal land grid array (LGA) package that meets the
demanding performance and board space requirements. The
device enables direct connection to high input voltages up to
18 V with no preregulators.
The switching frequency of the ADP5056 can be programmed
or synchronized to an external clock. The ADP5056 contains an
enable pin (ENx) on each channel for easy power-up sequencing
or adjustable undervoltage lockout (UVLO) threshold.
The ADP5056 integrates start-up/shutdown sequence control,
forced pulse-width modulation/power saving mode (FPWM/PSM)
selection, an output discharge switch, and a power-good signal.
All channels integrate both high-side and low-side power metal-
oxide semiconductor field effect transistors (MOSFETs) to achieve
an efficiency optimized solution. Channel 1 and Channel 2
deliver a programmable output current of 3.5 A or 7 A, or
provide a single output with up to 14 A of current in parallel
operation. Channel 3 delivers a programmable output current
of 1.5 A or 3 A.
The ADP5056 is rated at −40°C to +150°C junction temperature.
Note that throughout this data sheet, multifunction pins, such
as SYNC/MODE, are referred to either by the entire pin name
or by a single function of the pin, for example, SYNC, when
only that function is relevant.
Rev. 0
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