Integrated Power Solution with Quad Buck
Regulators and Supervisory Circuits
ADP5053
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
ADP5053
Wide input voltage range: 4.5 V to 15.0 V
SYNC/MODE
VREG
INT VREG
1.5% output accuracy over full temperature range
250 kHz to 1.4 MHz adjustable switching frequency
Adjustable/fixed output options via factory fuse
Power regulation
VDD
OSCILLATOR
RT
C1
100mA
C0
FB1
PVIN1
4.5V TO 15V
BST1
SW1
C3
L1
CHANNEL 1
BUCK REGULATOR
(1.2A/2.5A/4A)
VOUT1
C4
C2
COMP1
VREG
Channel 1 and Channel 2: programmable 1.2 A/2.5 A/4 A
sync buck regulators with low-side FET driver
Channel 3 and Channel 4: 1.2 A sync buck regulators
Single 8 A output (Channel 1 and Channel 2 operated in parallel)
Precision enable with 0.8 V accurate threshold
Active output discharge switch
FPWM or automatic PWM/PSM selection
Frequency synchronization input or output
Optional latch-off protection on OVP/OCP failure
Power-good flag on selected channels
UVLO, OCP, and TSD protection
Q1
Q2
EN1
DL1
SS12
R
ILIM1
PGND
DL2
R
ILIM2
PVIN2
C5
VREG
CHANNEL 2
BUCK REGULATOR
(1.2A/2.5A/4A)
VOUT2
C7
SW2
COMP2
L2
C6
C9
BST2
FB2
EN2
PWRGD
PVIN3
BST3
L3
C8
VOUT3
C10
SW3
CHANNEL 3
BUCK REGULATOR
(1.2A)
COMP3
EN3
FB3
PGND3
SS34
BST4
Open-drain processor reset with external adjustable
threshold monitoring
Watchdog refresh input
PVIN4
C12
L4
VOUT4
C13
SW4
FB4
CHANNEL 4
BUCK REGULATOR
(1.2A)
C11
COMP4
EN4
VREG
PGND4
RSTO
VTH
Manual reset input
WDI
MR
WATCHDOG
AND RESET
APPLICATIONS
VOUTx
Small cell base stations
FPGA and processor applications
Security and surveillance
Medical applications
EXPOSED PAD
Figure 1.
GENERAL DESCRIPTION
The ADP5053 combines four high performance buck regulators, a
supervisory circuit, a watchdog timer, and a manual reset in a
48-lead LFCSP package that meets demanding performance and
board space requirements. The device enables direct connection
to high input voltages up to 15.0 V with no preregulators.
The switching frequency of the ADP5053 can be programmed
or synchronized to an external clock. The ADP5053 contains a
precision enable pin on each channel for easy power-up sequencing
or adjustable UVLO threshold.
The ADP5053 contains supervisory circuits that monitor the
voltage level. The watchdog timer can generate a reset if the
WDI pin is not toggled within a preset timeout period. Processor
reset mode or system power on/off switch mode can be selected
for manual reset functionality.
Channel 1 and Channel 2 integrate high-side power MOSFET and
low-side MOSFET drivers. External NFETs can be used in low-side
power devices to achieve an efficiency optimized solution and
deliver a programmable output current of 1.2 A, 2.5 A, or 4 A.
Combining Channel 1 and Channel 2 in a parallel configuration
can provide a single output with up to 8 A of current.
Table 1. Family Models
Model
ADP5050 Four bucks, one LDO
ADP5051 Four bucks, supervisory
Channels
I2C
Package
Channel 3 and Channel 4 integrate both high-side and low-side
MOSFETs to deliver an output current of 1.2 A.
Yes 48-Lead LFCSP
Yes 48-Lead LFCSP
ADP5052 Four bucks, one LDO
ADP5053 Four bucks, supervisory
ADP5054 Four high current bucks
No
No
No
48-Lead LFCSP
48-Lead LFCSP
48-Lead LFCSP
Rev. C
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rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
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Tel: 781.329.4700 ©2013–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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