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ADP5041ACPZ-1-R7 PDF预览

ADP5041ACPZ-1-R7

更新时间: 2024-02-21 02:39:02
品牌 Logo 应用领域
亚德诺 - ADI PC
页数 文件大小 规格书
41页 3612K
描述
Micro PMU with 1.2 A Buck, Two 300 mA LDOs, Supervisory, Watchdog, and Manual Reset

ADP5041ACPZ-1-R7 技术参数

Source Url Status Check Date:2013-05-01 14:56:47.042是否无铅:含铅
是否Rohs认证:符合生命周期:Active
零件包装代码:QFN包装说明:HVQCCN, LCC20,.16SQ,20
针数:20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:1.69Samacsys Confidence:
Samacsys Status:ReleasedSamacsys PartID:577689
Samacsys Pin Count:21Samacsys Part Category:Integrated Circuit
Samacsys Package Category:OtherSamacsys Footprint Name:QFN50P400X400X80-21N
Samacsys Released Date:2017-01-10 13:33:33Is Samacsys:N
可调阈值:YES模拟集成电路 - 其他类型:POWER SUPPLY MANAGEMENT CIRCUIT
JESD-30 代码:S-XQCC-N20长度:4 mm
信道数量:1功能数量:1
端子数量:20最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:UNSPECIFIED
封装代码:HVQCCN封装等效代码:LCC20,.16SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED电源:2.5/5 V
认证状态:Not Qualified座面最大高度:0.8 mm
子类别:Power Management Circuits最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:DMOS
温度等级:AUTOMOTIVE端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4 mm
Base Number Matches:1

ADP5041ACPZ-1-R7 数据手册

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Micro PMU with 1.2 A Buck, Two 300 mA LDOs,  
Supervisory, Watchdog, and Manual Reset  
Data Sheet  
ADP5041  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
VOUT1  
Input voltage range: 2.3 V to 5.5 V  
One 1.2 A buck regulator  
Two 300 mA LDOs  
20-lead, 4 mm × 4 mm LFCSP package  
Overcurrent and thermal protection  
Soft start  
Undervoltage lockout  
Open-drain processor reset with externally adjustable  
threshold monitoring  
Guaranteed reset output valid to VAVIN = 1 V  
Manual reset input  
R
= 30  
FILT  
AVIN  
VIN1  
L1  
1µH  
SW  
V
AT  
OUT1  
1.2A  
FB1  
R1  
BUCK  
C6  
VBIAS  
10µF  
R2  
V
= 2.3V TO  
5.5V  
IN1  
PGND  
MODE  
C1  
4.7µF  
EN_BK  
ON  
ON  
ON  
FPWM  
R3  
EN1  
OFF  
PSM/PWM  
C5  
VOUT2  
FB2  
V
AT  
LDO1  
(DIGITAL)  
OUT2  
300mA  
VIN2  
V
= 1.7V  
IN2  
TO 5.5V  
C2  
1µF  
EN_LDO1  
2.2µF  
R4  
EN2  
MR  
OFF  
OFF  
nRSTO  
VBIAS  
µP  
WDI  
SUPERVISOR  
VTHR  
EN3  
R5  
R4  
Watchdog refresh input  
Buck key specifications  
Output voltage range: 0.8 V to 3.8 V  
Current mode topology for excellent transient response  
3 MHz operating frequency  
EN_LDO2  
VOUT3  
FB3  
VIN3  
V
AT  
OUT3  
300mA  
V
= 1.7V  
LDO2  
(ANALOG)  
IN3  
TO 5.5V  
C3  
1µF  
C6  
2.2µF  
R7  
R3  
AGND  
Figure 1.  
Peak efficiency up to 96%  
Uses tiny multilayer inductors and capacitors  
Mode pin selects forced PWM or auto PWM/PSM mode  
100% duty cycle low dropout mode  
LDOs key specifications  
Output voltage range: 0.8 V to 5.2 V  
Low input supply voltage from 1.7 V to 5.5 V  
Stable with 2.2 μF ceramic output capacitors  
High PSRR  
Low output noise  
Low dropout voltage  
−40°C to +125°C junction temperature range  
GENERAL DESCRIPTION  
The ADP5041 combines one high performance buck regulator  
and two low dropout regulators (LDO) in a small 20-lead  
LFCSP to meet demanding performance and board space  
requirements.  
range of the ADP5041 LDOs extend the battery life of portable  
devices. The ADP5041 LDOs maintain a power supply rejection  
greater than 60 dB for frequencies as high as 10 kHz while  
operating with a low headroom voltage.  
The high switching frequency of the buck regulator enables  
use of tiny multilayer external components and minimizes  
board space.  
Each regulator in the ADP5041 is activated by a high level on  
the respective enable pin. The output voltages of the regulators  
and the reset threshold are programmed through external resistor  
dividers to address a variety of applications. The ADP5041  
contains supervisory circuits that monitor power supply voltage  
levels and code execution integrity in microprocessor-based  
systems. They also provide power-on reset signals. An on-chip  
watchdog timer can reset the microprocessor if it fails to strobe  
within a preset timeout period.  
When the MODE pin is set to logic high, the buck regulator  
operates in forced PWM mode. When the MODE pin is set to  
logic low, the buck regulator operates in PWM mode when the  
load is around the nominal value. When the load current falls  
below a predefined threshold, the regulator operates in power  
save mode (PSM), improving the light load efficiency. The low  
quiescent current, low dropout voltage, and wide input voltage  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2011 Analog Devices, Inc. All rights reserved.  
 
 
 
 

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