Datasheet > 74LVX08T

74LVX08T

更新时间： 2024-09-09 23:24:31

品牌	Logo	应用领域
其他 - ETC		触发器逻辑集成电路光电二极管栅
页数	文件大小	规格书
8页	58K
描述
Quad 2-input AND Gate

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中文翻译

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数据手册

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74LVX08T 数据手册

74LVX08

LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE

■

HIGH SPEED:t_PD=4.8ns (TYP.) atV_CC= 3.3V

INPUT VOLTAGELEVEL:

V_IL=0.8V,V_IH=2V atV_CC=3V

LOW POWER DISSIPATION:

■

_CC=2 µA (MAX.) at T_A=25 ^oC

LOWNOISE:

(Micro Package)

(TSSOPPackage)

V_OLP=0.3 V (TYP.)at V_CC= 3.3V

SYMMETRICAL OUTPUT IMPEDANCE:

|I_OH| = I_OL= 4 mA (MIN)

BALANCEDPROPAGATIONDELAYS:

t_PLHt_PHL

ORDER CODES :

74LVX08M

74LVX08T

including buffer output, which enable high noise

immunity and stable output.

It has better speed performance at 3.3V than 5V

LS-TTL family combined with the true CMOS low

power consumption.

OPERATING VOLTAGERANGE:

V_CC(OPR)= 2V to 3.6V(1.2VDataRetention)

PIN AND FUNCTION COMPATIBLEWITH

74 SERIES08

IMPROVED LATCH-UP IMMUNITY

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

DESCRIPTION

The 74LVX08 is a low voltage CMOS QUAD

2-INPUT AND GATE fabricated with sub-micron

silicon gate and double-layermetal wiring C²MOS

technology.It is ideal for low power and low noise

3.3V applications.

The internal circuit is composed of 2 stages

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/8

March 1999

12 3 4 5 6 7 8

中文翻译

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与74LVX08T相关器件

型号	品牌	获取价格	描述	数据表
74LVX08TTR	STMICROELECTRONICS	获取价格	LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE WITH 5V TOLERANT INPUTS
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74LVX112M	FAIRCHILD	获取价格	Low Voltage Dual J-K Flip-Flops with Preset and Clear
74LVX112MTC	FAIRCHILD	获取价格	Low Voltage Dual J-K Flip-Flops with Preset and Clear
74LVX112MTCX	TI	获取价格	LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PD
74LVX112MX	TI	获取价格	LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PD
74LVX112SJ	FAIRCHILD	获取价格	Low Voltage Dual J-K Flip-Flops with Preset and Clear
74LVX112SJX	TI	获取价格	LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PD
74LVX125	FAIRCHILD	获取价格	Low Voltage Quad Buffer with 3-STATE Outputs
74LVX125	STMICROELECTRONICS	获取价格	LOW VOLTAGE QUAD BUS BUFFERS (3-STATE) WITH 5V TOLERANT INPUTS