74LVX112M

更新时间： 2024-09-09 22:15:07

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
7页	80K
描述
Low Voltage Dual J-K Flip-Flops with Preset and Clear

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数据手册

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74LVX112M 数据手册

October 1996

Revised December 2003

74LVX112

Low Voltage Dual J-K Flip-Flops with Preset and Clear

either state without affecting the flip-flop, provided that they

are in the desired state during the recommended setup and

hold times relative to the falling edge of the clock.

General Description

The LVX112 is a dual J-K Flip-Flop where each flip-flop has

independent inputs (J, K, PRESET, CLEAR, and CLOCK)

The inputs tolerate voltages up to 7V allowing the interface

and outputs (Q, Q). These devices are edge sensitive and

of 5V systems to 3V systems.

change states synchronously on the negative going transi-

tion of the clock pulse. Triggering occurs at a voltage level

of the clock and is not directly related to the transition time.

Clear and Preset are independent of the clock and are

accomplished by a low logic level on the corresponding

input. The J and K inputs can change when the clock is in

Features

■ Input voltage level translation from 5V–3V

■ Ideal for low power/low noise 3.3V applications

Ordering Code:

Order Number Package Number

Package Description

74LVX112M

M16A

M16D

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74LVX112SJ

74LVX112MTC

MTC16

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

J₁, J₂, K₁, K₂

CLK₁, CLK₂

CLR₁, CLR₂

PR₁, PR₂

Description

Data Inputs

Clock Pulse Inputs (Active Falling edge)

Direct Clear Inputs (Active LOW)

Direct Preset Inputs (Active LOW)

Q₁, Q₂, Q₁, Q₂

DS012158

www.fairchildsemi.com

12 3 4 5 6 7

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