Datasheet > 74LVC74AD

74LVC74AD

更新时间： 2024-11-20 11:12:43

品牌	Logo	应用领域
安世 - NEXPERIA		光电二极管逻辑集成电路触发器
页数	文件大小	规格书
16页	261K
描述
Dual D-type flip-flop with set and reset; positive-edge triggerProduction

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74LVC74AD 数据手册

74LVC74A

Dual D-type flip-flop with set and reset; positive-edge trigger

Rev. 9 — 20 August 2021

Product data sheet

1. General description

The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP)

inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock

input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition

of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock

transition, for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall

times.

2. Features and benefits

•

5 V tolerant inputs for interlacing with 5 V logic

•

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Direct interface with TTL levels

Complies with JEDEC standard:

•

JESD8-7A (1.65 V to 1.95 V)

JESD8-5A (2.3 V to 2.7 V)

JESD8-C/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-B exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

•

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC74AD

74LVC74APW

74LVC74ABQ

-40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

TSSOP14

plastic thin shrink small outline package; 14 leads; SOT402-1

body width 4.4 mm

DHVQFN14 plastic dual in-line compatible thermal enhanced

very thin quad flat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

SOT762-1

12 3 4 5 6 7...16

中文翻译

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与74LVC74AD相关器件

型号	品牌	获取价格	描述	数据表
74LVC74AD,112	NXP	获取价格	74LVC74A - Dual D-type flip-flop with set and reset; positive-edge trigger SOIC 14-Pin
74LVC74ADB	NXP	获取价格	Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74ADB,112	NXP	获取价格	74LVC74A - Dual D-type flip-flop with set and reset; positive-edge trigger SSOP1 14-Pin
74LVC74ADB-T	ETC	获取价格	Dual D-Type Flip-Flop
74LVC74AD-Q100	NEXPERIA	获取价格	Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74AD-Q100J	NXP	获取价格	74LVC74A-Q100 - Dual D-type flip-flop with set and reset; positive-edge trigger SOIC 14-Pi
74LVC74AD-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO1
74LVC74APW	NXP	获取价格	Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74APW	NEXPERIA	获取价格	Dual D-type flip-flop with set and reset; positive-edge triggerProduction
74LVC74APW,112	NXP	获取价格	74LVC74A - Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP 14-Pin

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