74LVC74D

更新时间： 2024-11-19 13:04:59

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
16页	104K
描述
暂无描述

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74LVC74D 数据手册

74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

Rev. 06 — 4 June 2007

Product data sheet

1. General description

The 74LVC74A is a dual edge triggered D-type ﬂip-ﬂop with individual data (D) inputs,

clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the

clock input. Information on the data input is transferred to the Q output on the

LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time

prior to the LOW-to-HIGH clock transition, for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and

fall times.

2. Features

I 5 V tolerant inputs for interlacing with 5 V logic

I Wide supply voltage range from 1.2 V to 3.6 V

I CMOS low power consumption

I Direct interface with TTL levels

I Complies with JEDEC standard JESD8-B/JESD36

I ESD protection:

N HBM JESD22-A114D exceeds 2000 V

N CDM JESD22-C101C exceeds 1000 V

I Speciﬁed from −40 °C to +85 °C and −40 °C to 125 °C

3. Ordering information

Table 1.

Type number Package

Temperature range Name

Ordering information

Description

Version

74LVC74AD

−40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74LVC74ADB −40 °C to +125 °C

74LVC74APW −40 °C to +125 °C

74LVC74ABQ −40 °C to +125 °C

SSOP14

TSSOP14

plastic shrink small outline package; 14 leads;

body width 5.3 mm

SOT337-1

SOT402-1

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1

quad ﬂat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

12 3 4 5 6 7...16

中文翻译

下载PDF

与74LVC74D相关器件

型号	品牌	获取价格	描述	数据表
74LVC74DB	PHILIPS	获取价格	D Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, PDSO14,
74LVC74DB	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO1
74LVC74DB-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO1
74LVC74D-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO1
74LVC74PW	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO1
74LVC821A	NXP	获取价格	10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State
74LVC821A_1	ETC	获取价格	10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
74LVC821A_2	ETC	获取价格	10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
74LVC821A_3	ETC	获取价格	10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
74LVC821ABQ	NXP	获取价格	10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state