Datasheet > 74LVC821A_1

74LVC821A_1

更新时间： 2024-11-19 12:54:27

品牌	Logo	应用领域
其他 - ETC		触发器
页数	文件大小	规格书
20页	123K
描述
10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

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74LVC821A_1 数据手册

74LVC821A

10-bit D-type ﬂip-ﬂop with 5 V tolerant inputs/outputs;

positive-edge trigger; 3-state

Rev. 03 — 11 May 2004

Product data sheet

1. General description

The 74LVC821A is a high performance, low power, low voltage Si-gate CMOS device and

superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can

handle 5 V. This feature allows the use of these devices as translators in a mixed 3.3 V

and 5 V environment.

The 74LVC821A is a 10-bit D-type ﬂip-ﬂop featuring separate D-type inputs for each

ﬂip-ﬂop and 3-state outputs for bus-oriented applications. A clock input (pin CP) and an

output enable input (pin OE) are common to all ﬂip-ﬂops. The ten ﬂip-ﬂops will store the

state of their individual D-inputs that meet the set-up and hold times requirements on the

LOW-to-HIGH CP transition. When pin OE is LOW, the contents of the ten ﬂip-ﬂops is

available at the outputs.

When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the

OE inputs does not affect the state of the ﬂip-ﬂops.

2. Features

■ 5 V tolerant inputs and outputs; for interfacing with 5 V logic

■ Wide supply voltage range from 1.2 V to 3.6 V

■ Inputs accept voltages up to 5.5 V

■ CMOS low power consumption

■ Direct interface with TTL levels

■ Flow-through pin-out architecture

■ 10-bit positive edge-triggered register

■ Independent register and 3-state buffer operation

■ Complies with JEDEC standard JESD8-B

■ ESD protection:

◆ HBM EIA/JESD22-A114-B exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V.

■ Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C.

12 3 4 5 6 7...20

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型号	品牌	获取价格	描述	数据表
74LVC821A_2	ETC	获取价格	10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
74LVC821A_3	ETC	获取价格	10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
74LVC821ABQ	NXP	获取价格	10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state
74LVC821ABQ,115	NXP	获取价格	74LVC821A - 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigge
74LVC821ABQ,118	NXP	获取价格	74LVC821A - 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigge
74LVC821AD	NXP	获取价格	10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State
74LVC821AD,118	NXP	获取价格	74LVC821A - 10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigge
74LVC821ADB	NXP	获取价格	10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State
74LVC821ADB-T	ETC	获取价格	10-Bit D-Type Flip-Flop
74LVC821AD-T	ETC	获取价格	10-Bit D-Type Flip-Flop