Datasheet > 74LVC823ABQ-Q100

74LVC823ABQ-Q100

更新时间： 2024-11-20 01:18:19

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
16页	239K
描述
9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74LVC823ABQ-Q100 数据手册

74LVC823A-Q100

9-bit D-type flip-flop with 5 V tolerant inputs/outputs;

positive edge-trigger; 3-state

Rev. 2 — 1 May 2019

Product data sheet

1. General description

The 74LVC823A-Q100 is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE),

master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops

stores the state of their individual D-inputs that meet the set-up and hold times requirements on the

LOW to HIGH CP transition, provided pin CE is LOW. When pin CE is HIGH, the flip-flops hold their

data. A LOW on pin MR resets all flip-flops. When pin OE is LOW, the contents of the 9 flip-flops

are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance

OFF-state. Operation of the OE input does not affect the state of the flip-flops.

Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied

to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V

applications.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

5 V tolerant inputs/outputs for interfacing with 5 V logic

Wide supply voltage range from 1.2 V to 3.6 V

CMOS low power consumption

Direct interface with TTL levels

Flow-through pinout architecture

9-bit positive edge-triggered register

Independent register and 3-state buffer operation

Complies with JEDEC standard:

•

JESD8-7A (1.65 V to 1.95 V)

JESD8-5A (2.3 V to 2.7 V)

JESD8-C/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC823ABQ-Q100 -40 °C to +125 °C

DHVQFN24 plastic dual in-line compatible thermal

enhanced very thin quad flat package; no leads;

24 terminals; body 3.5 × 5.5 × 0.85 mm

SOT815-1

12 3 4 5 6 7...16

中文翻译

下载PDF

与74LVC823ABQ-Q100相关器件

型号	品牌	获取价格	描述	数据表
74LVC823AD	NXP	获取价格	9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State
74LVC823AD	PHILIPS	获取价格	D Flip-Flop, 9-Func, Positive Edge Triggered, CMOS, PDSO24
74LVC823ADB	NXP	获取价格	9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State
74LVC823ADB,112	NXP	获取价格	74LVC823A - 9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger
74LVC823ADB-T	ETC	获取价格	9-Bit D-Type Flip-Flop
74LVC823AD-T	ETC	获取价格	9-Bit D-Type Flip-Flop
74LVC823APW	NXP	获取价格	9-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State
74LVC823APW,112	NXP	获取价格	74LVC823A - 9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger
74LVC823APW-T	ETC	获取价格	9-Bit D-Type Flip-Flop
74LVC823A-Q100	NEXPERIA	获取价格	9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

与74LVC823ABQ-Q100相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

23
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

15
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

45
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

45

产品中心

服务支持

精选活动

关于我们

帮助中心

74LVC823ABQ-Q100

74LVC823ABQ-Q100 数据手册

与74LVC823ABQ-Q100相关器件

与74LVC823ABQ-Q100相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

74LVC823ABQ-Q100

74LVC823ABQ-Q100 数据手册

与74LVC823ABQ-Q100相关器件

与74LVC823ABQ-Q100相关文章

您还可以找

您在本页遇到什么问题？