Datasheet > 74LVC74APW-Q100J

74LVC74APW-Q100J

更新时间： 2024-11-19 18:30:35

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
18页	140K
描述
74LVC74A-Q100 - Dual D-type flip-flop with set and reset; positive-edge trigger TSSOP 14-Pin

阅读下载

中文翻译

获取价格

如果您发现信息不准确，欢迎纠错

74LVC74APW-Q100J 技术参数

74LVC74A-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

Rev. 2 — 5 April 2013

Product data sheet

1. General description

The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop. It has individual data (nD)

inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ

outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the

clock input. Information on the data input is transferred to the nQ output on the

LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time

prior to the LOW-to-HIGH clock transition, for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and

fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 5 V tolerant inputs for interlacing with 5 V logic

 Wide supply voltage range from 1.2 V to 3.6 V

 CMOS low power consumption

 Direct interface with TTL levels

 ESD protection:

 MIL-STD-883, method 3015 exceeds 2000 V

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Multiple package options

12 3 4 5 6 7...18

中文翻译

下载PDF

型号	品牌	获取价格	描述	数据表
74LVC74APW-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO1
74LVC74A-Q100	NEXPERIA	获取价格	Dual D-type flip-flop with set and reset; positive-edge trigger
74LVC74D	NXP	获取价格	暂无描述
74LVC74DB	PHILIPS	获取价格	D Flip-Flop, 2-Func, Positive Edge Triggered, CMOS, PDSO14,
74LVC74DB	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO1
74LVC74DB-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO1
74LVC74D-T	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO1
74LVC74PW	NXP	获取价格	IC LVC/LCX/Z SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO1
74LVC821A	NXP	获取价格	10-bit D-type flip-flop with 5-volt tolerant inputs/outputs; positive-edge trigger 3-State
74LVC821A_1	ETC	获取价格	10-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive-edge trigger; 3-state