5秒后页面跳转
74LV08D PDF预览

74LV08D

更新时间: 2024-11-22 11:11:27
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
11页 213K
描述
Quad 2-input AND gateProduction

74LV08D 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:SOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:2.16
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
逻辑集成电路类型:AND GATE湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
传播延迟(tpd):33 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

74LV08D 数据手册

 浏览型号74LV08D的Datasheet PDF文件第2页浏览型号74LV08D的Datasheet PDF文件第3页浏览型号74LV08D的Datasheet PDF文件第4页浏览型号74LV08D的Datasheet PDF文件第5页浏览型号74LV08D的Datasheet PDF文件第6页浏览型号74LV08D的Datasheet PDF文件第7页 
74LV08  
Quad 2-input AND gate  
Rev. 5 — 13 September 2021  
Product data sheet  
1. General description  
The 74LV08 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of  
current limiting resistors to interface inputs to voltages in excess VCC  
.
2. Features and benefits  
Wide supply voltage range from 1.0 to 5.5 V  
CMOS low power dissipation  
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B  
Optimized for low voltage applications: 1.0 V to 3.6 V  
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V  
Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 °C  
Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 °C  
Complies with JEDEC standards:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
JESD36 (4.5 V to 5.5 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LV08D  
-40 °C to +125 °C  
SO14  
plastic small outline package; 14 leads;  
body width 3.9 mm  
SOT108-1  
74LV08PW  
-40 °C to +125 °C  
TSSOP14  
plastic thin shrink small outline package; 14 leads;  
body width 4.4 mm  
SOT402-1  
 
 
 

与74LV08D相关器件

型号 品牌 获取价格 描述 数据表
74LV08DB NXP

获取价格

Quad 2-input AND gate
74LV08DB,112 NXP

获取价格

74LV08 - Quad 2-input AND gate SSOP1 14-Pin
74LV08DB,118 NXP

获取价格

74LV08 - Quad 2-input AND gate SSOP1 14-Pin
74LV08DB-T ETC

获取价格

Quad 2-input AND Gate
74LV08D-Q100 NEXPERIA

获取价格

Quad 2-input AND gate
74LV08D-T ETC

获取价格

Quad 2-input AND Gate
74LV08N NXP

获取价格

Quad 2-input AND gate
74LV08N,112 NXP

获取价格

74LV08N
74LV08PW NEXPERIA

获取价格

Quad 2-input AND gateProduction
74LV08PW NXP

获取价格

Quad 2-input AND gate