Datasheet > 74LV08PW

74LV08PW

更新时间： 2024-10-01 11:11:27

品牌	Logo	应用领域
安世 - NEXPERIA		栅光电二极管逻辑集成电路触发器
页数	文件大小	规格书
11页	213K
描述
Quad 2-input AND gateProduction

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74LV08PW 数据手册

74LV08

Quad 2-input AND gate

Rev. 5 — 13 September 2021

Product data sheet

1. General description

The 74LV08 is a quad 2-input AND gate. Inputs include clamp diodes. This enables the use of

current limiting resistors to interface inputs to voltages in excess V_CC

2. Features and benefits

•

Wide supply voltage range from 1.0 to 5.5 V

CMOS low power dissipation

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

Optimized for low voltage applications: 1.0 V to 3.6 V

Accepts TTL input levels between V_CC= 2.7 V and V_CC= 3.6 V

Typical output ground bounce < 0.8 V at V_CC= 3.3 V and T_amb= 25 °C

Typical HIGH-level output voltage (V_OH) undershoot: > 2 V at V_CC= 3.3 V and T_amb= 25 °C

Complies with JEDEC standards:

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

JESD36 (4.5 V to 5.5 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LV08D

-40 °C to +125 °C

SO14

plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74LV08PW

-40 °C to +125 °C

TSSOP14

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

12 3 4 5 6 7...11

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与74LV08PW相关器件

型号	品牌	获取价格	描述	数据表
74LV08PWDH	NXP	获取价格	Quad 2-input AND gate
74LV08PW-Q100	NEXPERIA	获取价格	Quad 2-input AND gate
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74LV08-Q100	NEXPERIA	获取价格	Quad 2-input AND gate
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74LV107D	NXP	获取价格	Dual JK flip-flop with reset; negative-edge trigger
74LV107D	PHILIPS	获取价格	J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, PDSO14,
74LV107DB	NXP	获取价格	Dual JK flip-flop with reset; negative-edge trigger
74LV107DB-T	ETC	获取价格	J-K-Type Flip-Flop