型号 | 品牌 | 获取价格 | 描述 | 数据表 |
74LV10 | NXP |
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Triple 3-input NAND gate | |
74LV107 | NXP |
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Dual JK flip-flop with reset; negative-edge trigger | |
74LV107D | NXP |
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Dual JK flip-flop with reset; negative-edge trigger | |
74LV107D | PHILIPS |
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J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, PDSO14, | |
74LV107DB | NXP |
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Dual JK flip-flop with reset; negative-edge trigger | |
74LV107DB-T | ETC |
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J-K-Type Flip-Flop | |
74LV107D-T | ETC |
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J-K-Type Flip-Flop | |
74LV107N | NXP |
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Dual JK flip-flop with reset; negative-edge trigger | |
74LV107PW | NXP |
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Dual JK flip-flop with reset; negative-edge trigger | |
74LV107PWDH | NXP |
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Dual JK flip-flop with reset; negative-edge trigger |