是否Rohs认证: | 不符合 | 生命周期: | Transferred |
包装说明: | SOP, SOP14,.25 | Reach Compliance Code: | unknown |
风险等级: | 5.83 | Is Samacsys: | N |
JESD-30 代码: | R-PDSO-G14 | JESD-609代码: | e0 |
负载电容(CL): | 50 pF | 逻辑集成电路类型: | J-K FLIP-FLOP |
最大频率@ Nom-Sup: | 20000000 Hz | 最大I(ol): | 0.006 A |
功能数量: | 2 | 端子数量: | 14 |
最高工作温度: | 125 °C | 最低工作温度: | -40 °C |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | SOP |
封装等效代码: | SOP14,.25 | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE | 电源: | 3.3 V |
Prop。Delay @ Nom-Sup: | 33 ns | 认证状态: | Not Qualified |
子类别: | FF/Latches | 标称供电电压 (Vsup): | 3.3 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | AUTOMOTIVE | 端子面层: | Tin/Lead (Sn/Pb) |
端子形式: | GULL WING | 端子节距: | 1.27 mm |
端子位置: | DUAL | 触发器类型: | NEGATIVE EDGE |
Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
74LV107DB | NXP |
获取价格 |
Dual JK flip-flop with reset; negative-edge trigger | |
74LV107DB-T | ETC |
获取价格 |
J-K-Type Flip-Flop | |
74LV107D-T | ETC |
获取价格 |
J-K-Type Flip-Flop | |
74LV107N | NXP |
获取价格 |
Dual JK flip-flop with reset; negative-edge trigger | |
74LV107PW | NXP |
获取价格 |
Dual JK flip-flop with reset; negative-edge trigger | |
74LV107PWDH | NXP |
获取价格 |
Dual JK flip-flop with reset; negative-edge trigger | |
74LV107PWDH-T | NXP |
获取价格 |
IC LV/LV-A/LVX/H SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, | |
74LV107PW-T | ETC |
获取价格 |
J-K-Type Flip-Flop | |
74LV109 | NXP |
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Dual JK flip-flop with set and reset; positive-edge trigger | |
74LV109D | NXP |
获取价格 |
Dual JK flip-flop with set and reset; positive-edge trigger |