生命周期: | Obsolete | 零件包装代码: | TSSOP |
包装说明: | TSSOP, | 针数: | 14 |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.13 | Is Samacsys: | N |
系列: | LV/LV-A/LVX/H | JESD-30 代码: | R-PDSO-G14 |
JESD-609代码: | e4 | 长度: | 5 mm |
负载电容(CL): | 50 pF | 逻辑集成电路类型: | AND GATE |
功能数量: | 4 | 输入次数: | 2 |
端子数量: | 14 | 最高工作温度: | 125 °C |
最低工作温度: | -40 °C | 封装主体材料: | PLASTIC/EPOXY |
封装代码: | TSSOP | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | 传播延迟(tpd): | 33 ns |
认证状态: | Not Qualified | 座面最大高度: | 1.1 mm |
最大供电电压 (Vsup): | 5.5 V | 最小供电电压 (Vsup): | 1 V |
标称供电电压 (Vsup): | 3.3 V | 表面贴装: | YES |
技术: | CMOS | 温度等级: | AUTOMOTIVE |
端子面层: | NICKEL PALLADIUM GOLD | 端子形式: | GULL WING |
端子节距: | 0.65 mm | 端子位置: | DUAL |
宽度: | 4.4 mm | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
74LV08PW-Q100 | NEXPERIA |
获取价格 |
Quad 2-input AND gate | |
74LV08PW-T | ETC |
获取价格 |
Quad 2-input AND Gate | |
74LV08-Q100 | NEXPERIA |
获取价格 |
Quad 2-input AND gate | |
74LV10 | NXP |
获取价格 |
Triple 3-input NAND gate | |
74LV107 | NXP |
获取价格 |
Dual JK flip-flop with reset; negative-edge trigger | |
74LV107D | NXP |
获取价格 |
Dual JK flip-flop with reset; negative-edge trigger | |
74LV107D | PHILIPS |
获取价格 |
J-K Flip-Flop, 2-Func, Negative Edge Triggered, CMOS, PDSO14, | |
74LV107DB | NXP |
获取价格 |
Dual JK flip-flop with reset; negative-edge trigger | |
74LV107DB-T | ETC |
获取价格 |
J-K-Type Flip-Flop | |
74LV107D-T | ETC |
获取价格 |
J-K-Type Flip-Flop |