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ZL30407/QCC PDF预览

ZL30407/QCC

更新时间： 2024-09-13 15:58:55
品牌 Logo 应用领域
美高森美 - MICROSEMI ATM异步传输模式电信电信集成电路
页数 文件大小 规格书
54页 768K
描述
ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, LQFP-80

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ZL30407/QCC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：80
Reach Compliance Code：compliant风险等级：5.24
JESD-30 代码：S-PQFP-G80JESD-609代码：e0
长度：14 mm湿度敏感等级：3
功能数量：1端子数量：80
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE
峰值回流温度（摄氏度）：240认证状态：Not Qualified
座面最大高度：1.6 mm标称供电电压：3.3 V
表面贴装：YES电信集成电路类型：SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

ZL30407/QCC 数据手册

 浏览型号ZL30407/QCC的Datasheet PDF文件第2页浏览型号ZL30407/QCC的Datasheet PDF文件第3页浏览型号ZL30407/QCC的Datasheet PDF文件第4页浏览型号ZL30407/QCC的Datasheet PDF文件第5页浏览型号ZL30407/QCC的Datasheet PDF文件第6页浏览型号ZL30407/QCC的Datasheet PDF文件第7页 
ZL30407  
SONET/SDH Network Element PLL  
Data Sheet  
April 2003  
Features  
•
Meets requirements of GR-253 for SONET  
Stratum 3 and SONET Minimum Clocks (SMC)  
Meets requirements of GR-1244 for Stratum 3  
Ordering Information  
•
•
Meets requirements of G.813 Option 1 and 2 for  
SDH Equipment Clocks (SEC)  
ZL30407/QCC 80 Pin LQFP  
•
•
•
Generates clocks for ST-BUS, DS1, DS2, DS3,  
OC-3, E1, E3, STM-1 and 19.44 MHz  
-40°C to +85°C  
Meets holdover accuracy of GR-1244 Stratum 3E  
and ITU-T G.812 (better than 1x10 -12  
)
Description  
Continuously monitors both references for  
frequency accuracy exceeding ±12 ppm  
The ZL30407 is a Network Element Phase-Locked  
Loop designed to synchronize SDH and SONET  
systems. In addition, it generates multiple clocks for  
legacy PDH equipment and provides timing for ST-BUS  
and GCI backplanes.  
•
•
Provides “hit-less” reference switching  
Compensates for Master Clock Oscillator  
accuracy  
•
Detects frequency of both reference clocks and  
synchronizes to any combination of 8 kHz, 1.544  
MHz, 2.048 MHz and 19.44 MHz reference  
frequencies.  
The ZL30407 operates in NORMAL (LOCKED),  
HOLDOVER and FREE-RUN modes to ensure that in  
the presence of jitter, wander and interruptions to the  
reference signals, the generated clocks meet  
international standards. The filtering characteristics of  
the PLL are hardware or software selectable and they  
do not require any external adjustable components.  
The ZL30407 uses an external 20 MHz Master Clock  
Oscillator to provide a stable timing source for the  
HOLDOVER operation.  
•
•
Allows Hardware or Microprocessor control  
Pin compatible with ZL30402 and MT90401.  
Applications  
•
Synchronization for SDH and SONET Network  
Elements  
•
Clock generation for ST-BUS and GCI backplanes  
The ZL30407 operates from a single 3.3 V power  
supply and offers a 5 V tolerant microprocessor  
interface.  
VDD GND  
C20i  
FCS  
OE  
C155P/N  
C34/C44  
C19o  
Master Clock  
Frequency  
Calibration  
APLL  
Clock  
C16o  
Primary  
Acquisition  
PLL  
PRI  
PRIOR  
C8o  
C6o  
C4o  
Synthesizer  
C2o  
Core PLL  
MUX  
C1.5o  
F16o  
F8o  
SEC  
SECOR  
Secondary  
Acquisition  
PLL  
F0o  
E3DS3/OC3  
RefSel  
E3/DS3  
Tclk  
Tdi  
JTAG  
HW  
IEEE  
Control State Machine  
Microport  
Tdo  
Tms  
1149.1a  
RESET  
Trst  
A0-A6 D0-D7  
M02  
CS DS R/W  
MS1 MS2 RefAlign LOCK HOLDOVER  
Figure 1 - Functional Block Diagram  
1
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