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ZL30410QCC PDF预览

ZL30410QCC

更新时间： 2024-10-29 22:07:03
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 电信集成电路异步传输模式ATM
页数 文件大小 规格书
38页 401K
描述
Multi-service Line Card PLL

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中文翻译

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ZL30410QCC 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：LQFP, QFP80,.64SQReach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.86
Is Samacsys：N应用程序：SONET;SDH
JESD-30 代码：S-PQFP-G80JESD-609代码：e0
长度：14 mm湿度敏感等级：3
功能数量：1端子数量：80
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP80,.64SQ封装形状：SQUARE
封装形式：FLATPACK, LOW PROFILE峰值回流温度（摄氏度）：240
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm子类别：Other Telecom ICs
最大压摆率：0.155 mA标称供电电压：3.3 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH SUPPORT CIRCUIT
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

ZL30410QCC 数据手册

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ZL30410  
Multi-service Line Card PLL  
Data Sheet  
November 2003  
Features  
•
•
•
Generates clocks for OC-3, STM-1, DS3, E3,  
DS2, DS1, E1, 19.44 MHz and ST-BUS  
Ordering Information  
Meets jitter generation requirements for STM-1,  
OC-3, DS3, E3, J2 (DS2), E1 and DS1 interfaces  
ZL30410QCC  
80 Pin LQFP  
Compatible with GR-253-CORE SONET stratum  
3 and G.813 SEC timing compliant clocks  
-40°C to 85°C  
•
•
Provides “hit-less” reference switching  
•
Clock generation for ST-BUS and GCI timing  
Detects frequency of both reference clocks and  
synchronizes to any combination of 8 kHz, 1.544  
MHz, 2.048 MHz and 19.44 MHz reference  
frequencies  
Description  
The ZL30410 is  
a
Multi-service Line Card  
•
•
•
Continuously monitors both references for  
frequency accuracy exceeding ±12 ppm  
Holdover accuracy of 70x10 -12 meets GR-1244  
Stratum 3E and ITU-T G.812 requirements  
Phase-Locked Loop designed to generate multiple  
clocks for SONET, SDH and PDH equipment including  
timing for ST-BUS and GCI interfaces.  
Meets requirements of G.813 Option 1 for SDH  
Equipment Clocks (SEC) and GR-1244 for  
Stratum 4E and Stratum 4 Clocks  
The ZL30410 operates in NORMAL (LOCKED),  
HOLDOVER and FREE-RUN modes to ensure that in  
the presence of jitter and interruptions to the reference  
signals, the generated clocks meet international  
standards. The filtering characteristics of the PLL are  
hardware pin selectable and they do not require any  
external adjustable components. The ZL30410 uses an  
external 20 MHz Master Clock Oscillator to provide a  
stable timing source for the HOLDOVER operation.  
•
3.3V power supply  
Applications  
•
Line Card synchronization for SDH, SONET, DS3,  
E3, J2 (DS2), E1 and DS1 interfaces  
•
Timing card synchronization for SDH and PDH  
Network Elements  
VDD GND  
C20i  
FCS  
OE  
C155P/N  
C34/C44  
C19o  
C16o  
C8o  
C6o  
C4o  
C2o  
C1.5o  
Master Clock  
Frequency  
Calibration  
APLL  
Clock  
Primary  
Acquisition  
PLL  
PRI  
PRIOR  
Synthesizer  
MUX  
Core PLL  
F16o  
F8o  
F0o  
SEC  
Secondary  
Acquisition  
PLL  
SECOR  
E3DS3/OC3  
E3/DS3  
RefSel  
Tclk  
Tdi  
Tdo  
Tms  
JTAG  
IEEE  
1149.1a  
RESET  
Control State Machine  
Trst  
MS1 MS2  
RefAlign  
LOCK HOLDOVER  
07  
Figure 1 - Functional Block Diagram  
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,  
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.  
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