ZL30414
SONET/SDH Clock Multiplier PLL
Data Sheet
February 2005
Features
•
Meets jitter requirements of Telcordia GR-253-
Ordering Information
CORE for OC-192, OC-48, OC-12, and OC-3
rates
ZL30414QGC 64 Pin TQFP Trays
ZL30414QGC1 64 Pin TQFP* Trays
*Pb Free Matte Tin
•
•
Meets jitter requirements of ITU-T G.813 for STM-
64, STM-16, STM-4 and STM-1 rates
-40°C to +85°C
Provides four LVPECL differential output clocks at
622.08 MHz
Description
•
•
Provides a CML differential clock at 155.52 MHz
The ZL30414 is an analog phase-locked loop (APLL)
designed to provide jitter attenuation and rate
conversion for SDH (Synchronous Digital Hierarchy)
and SONET (Synchronous Optical Network)
networking equipment. The ZL30414 generates very
low jitter clocks that meet the jitter requirements of
Telcordia GR-253-CORE OC-192, OC-48, OC-12, OC-
3 rates and ITU-T G.813 STM-64, STM-16, STM-4 and
STM-1 rates.
Provides a single-ended CMOS clock at 19.44
MHz
•
•
•
•
Lock Indicator
Provides enable/disable control of output clocks
Accepts a CMOS reference at 19.44 MHz
3.3 V supply
Applications
•
•
The ZL30414 accepts a CMOS compatible reference
at 19.44 MHz and generates four LVPECL differential
output clocks at 622.08 MHz, a CML differential
clock at 155.52 MHz and a single-ended CMOS
clock at 19.44 MHz. The output clocks can be
individually enabled or disabled. The ZL30414
provides a LOCK indication.
SONET/SDH line cards
Network Element timing cards
C622oEN-A
C622oEN-B
C622oEN-C
C622oEN-D
LPF
C622oP/N-A
Frequency
& Phase
Detector
C19i
C622oP/N-B
Frequency
Loop
Filter
VCO
Dividers
and
C622oP/N-C
C622oP/N-D
C155oP/N
C19o
Clock
Drivers
19.44MHz
Reference
and
State
Machine
Bias Circuit
C155oEN
C19oEN
VDD GND VCC
LOCK
BIAS
05
Figure 1 - Functional Block Diagram
1
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