Datasheet > ZL30410QGG1

ZL30410QGG1

更新时间： 2024-10-30 14:45:47

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		/
页数	文件大小	规格书
39页	436K
描述
Support Circuit, 1-Func, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80

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ZL30410QGG1 技术参数

生命周期：	Transferred	包装说明：	LQFP,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.8	JESD-30 代码：	S-PQFP-G80
JESD-609代码：	e3	长度：	14 mm
功能数量：	1	端子数量：	80
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE
认证状态：	Not Qualified	座面最大高度：	1.6 mm
标称供电电压：	3.3 V	表面贴装：	YES
电信集成电路类型：	ATM/SONET/SDH SUPPORT CIRCUIT	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

ZL30410QGG1 数据手册

ZL30410

Multi-service Line Card PLL

Data Sheet

March 2006

Features

•

Generates clocks for OC-3, STM-1, DS3, E3,

DS2, DS1, E1, 19.44 MHz and ST-BUS

Ordering Information

ZL30410QCC

ZL30410QGG1

ZL30410QCG1

80 Pin LQFP Trays

80 Pin LQFP*Trays, Bake & Drypack

80 Pin LPFP*Trays, Bake & Drypack

Meets jitter generation requirements for STM-1,

OC-3, DS3, E3, J2 (DS2), E1 and DS1 interfaces

Compatible with GR-253-CORE SONET stratum

3 and G.813 SEC timing compliant clocks

*Pb Free Matte Tin

-40°C to 85°C

•

Provides “hit-less” reference switching

•

Clock generation for ST-BUS and GCI timing

Detects frequency of both reference clocks and

synchronizes to any combination of 8 kHz,

1.544 MHz, 2.048 MHz and 19.44 MHz reference

frequencies

Description

The ZL30410 is

Multi-service Line Card

•

Continuously monitors both references for

frequency accuracy exceeding ±12 ppm

Holdover accuracy of 70x10 ^-12meets GR-1244

Stratum 3E and ITU-T G.812 requirements

Phase-Locked Loop designed to generate multiple

clocks for SONET, SDH and PDH equipment including

timing for ST-BUS and GCI interfaces.

Meets requirements of G.813 Option 1 for SDH

Equipment Clocks (SEC) and GR-1244 for

Stratum 4E and Stratum 4 Clocks

The ZL30410 operates in NORMAL (LOCKED),

HOLDOVER and FREE-RUN modes to ensure that in

the presence of jitter and interruptions to the reference

signals, the generated clocks meet international

standards. The filtering characteristics of the PLL are

hardware pin selectable and they do not require any

external adjustable components. The ZL30410 uses an

external 20 MHz Master Clock Oscillator to provide a

stable timing source for the HOLDOVER operation.

•

3.3 V power supply

Applications

•

Line Card synchronization for SDH, SONET, DS3,

E3, J2 (DS2), E1 and DS1 interfaces

•

Timing card synchronization for SDH and PDH

Network Elements

VDD GND

C20i

FCS

C155P/N

C34/C44

C19o

C16o

C8o

C6o

C4o

C2o

C1.5o

Master Clock

Frequency

Calibration

APLL

Clock

Primary

Acquisition

PLL

PRI

PRIOR

Synthesizer

MUX

Core PLL

F16o

F8o

F0o

SEC

Secondary

Acquisition

PLL

SECOR

E3DS3/OC3

E3/DS3

RefSel

Tclk

Tdi

Tdo

Tms

JTAG

IEEE

1149.1a

RESET

Control State Machine

Trst

MS1 MS2

RefAlign

LOCK HOLDOVER

Figure 1 - Functional Block Diagram

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,

France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...39

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与ZL30410QGG1相关器件

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ZL30414	ZARLINK	获取价格	SONET/SDH Clock Multiplier PLL
ZL30414QGC	ZARLINK	获取价格	SONET/SDH Clock Multiplier PLL
ZL30414QGC1	ZARLINK	获取价格	SONET/SDH Clock Multiplier PLL
ZL30414QGG1	ZARLINK	获取价格	Support Circuit, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64
ZL30414QGG1	MICROSEMI	获取价格	Support Circuit, 1-Func, PQFP64, 10 X 10 MM, 1 MM HEIGHT, LEAD FREE, MS-026ACD, TQFP-64
ZL30415	ZARLINK	获取价格	SONET/SDH Clock Multiplier PLL
ZL30415_06	ZARLINK	获取价格	SONET/SDH Clock Multiplier PLL
ZL30415GGC	ZARLINK	获取价格	SONET/SDH Clock Multiplier PLL
ZL30415GGF	ZARLINK	获取价格	SONET/SDH Clock Multiplier PLL
ZL30415GGF2	ZARLINK	获取价格	SONET/SDH Clock Multiplier PLL

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