Datasheet > ZL30409_06

ZL30409_06

更新时间： 2024-10-30 03:08:35

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		/
页数	文件大小	规格书
32页	412K
描述
T1/E1 System Synchronizer with Stratum 3 Holdover

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ZL30409_06 数据手册

ZL30409

T1/E1 System Synchronizer

with Stratum 3 Holdover

Data Sheet

April 2006

Features

•

Supports Telcordia GR-1244-CORE Stratum 4

Ordering Information

timing for DS1 interfaces

ZL30409/DDE 48 Pin SSOP

Tubes

Supports ETSI ETS 300 011, TBR 4, TBR 12 and

TBR 13 timing for E1 interfaces

ZL30409/DDF 48 Pin SSOP

Tape & Reel

ZL30409DDE1 48 Pin SSOP* Tubes, Bake & Drypack

ZL30409DDF1 48 Pin SSOP* Tape & Reel,

Bake & Drypack

Selectable 19.44 MHz, 2.048 MHz, 1.544 MHz or

8 kHz input reference signals

Provides C1.5, C2, C4, C6, C8, C16, and C19

(STS-3/OC3 clock divided by 8) output clock

signals

*Pb Free Matte Tin

-40°C to +85°C

Applications

•

Synchronization and timing control for multitrunk

T1,E1 and STS-3/OC3 systems

•

Provides 5 styles of 8 KHz framing pulses

Holdover frequency accuracy of 0.05 PPM

Holdover indication

Attenuates wander from 1.9 Hz

Fast lock mode

•

ST-BUS clock and frame pulse sources

Description

The ZL30409 T1/E1 System Synchronizer contains a

digital phase-locked loop (DPLL), which provides timing

and synchronization signals for multitrunk T1 and E1

primary rate transmission links.

Provides Time Interval Error (TIE) correction

Accepts reference inputs from two independent

sources

The ZL30409 generates ST-BUS clock and framing

signals that are phase locked to either a 19.44 MHz,

2.048 MHz, 1.544 MHz, or 8 kHz input reference.

•

JTAG Boundary Scan

LOCK

OSCi

OSCo

TCLR

V_DD

GND

Virtual

Master Clock

Reference

C19o

TIE

TCK

TDI

C1.5o

Corrector

Circuit

DPLL

IEEE

C2o

TMS

TRST

TDO

1149.1a

C4o

Output

C6o

C8o

C16o

F0o

Interface

Circuit

Selected

Reference

State

Select

Reference

Select

PRI

SEC

F8o

Input

MUX

F16o

Impairment

Monitor

RSP

State

TIE

TSP

Select

Reference

Select

Corrector

Enable

Frequency

Select

Feedback

RSEL

Control State Machine

MUX

MS1 MS2

RST HOLDOVER PCCi FLOCK

FS1

FS2

Figure 1 - Functional Block Diagram

Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,

France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

12 3 4 5 6 7...32

中文翻译

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与ZL30409_06相关器件

型号	品牌	获取价格	描述	数据表
ZL30409DDA1	ZARLINK	获取价格	Telecom Circuit, 1-Func, PDSO48, 0.300 INCH, LEAD FREE, MO-118AA, SSOP-48
ZL30409DDB1	ZARLINK	获取价格	Telecom Circuit, 1-Func, PDSO48, 0.300 INCH, MO-118AA, SSOP-48
ZL30409DDB1	MICROSEMI	获取价格	SPECIALTY TELECOM CIRCUIT, PDSO48, 0.300 INCH, MO-118AA, SSOP-48
ZL30409DDE1	ZARLINK	获取价格	T1/E1 System Synchronizer with Stratum 3 Holdover
ZL30409DDF1	ZARLINK	获取价格	T1/E1 System Synchronizer with Stratum 3 Holdover
ZL30410	ZARLINK	获取价格	Multi-service Line Card PLL
ZL30410_06	ZARLINK	获取价格	Multi-service Line Card PLL
ZL30410QCC	ZARLINK	获取价格	Multi-service Line Card PLL
ZL30410QCC1	ZARLINK	获取价格	Support Circuit, 1-Func, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, LQFP-80
ZL30410QCG1	ZARLINK	获取价格	Multi-service Line Card PLL

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